Cypress CY7C68000A specifications MoBL-USBTX2 Features, Logic Block Diagram, Vfbga

CY7C68000A

MoBL-USB™ TX2 USB 2.0 UTMI Transceiver

MoBL-USB™TX2 Features

■UTMI-compliant and USB 2.0 certified for device operation

■Operates in both USB 2.0 High Speed (HS), 480 Mbits/second, and Full Speed (FS), 12 Mbits/second

■Optimized for Seamless Interface with Intel® Monahans Appli- cations Processors

■Tri-state Mode enables sharing of UTMI Bus with other devices

■Serial-to-Parallel and Parallel-to-Serial Conversions

■8-bit Unidirectional, 8-bit Bidirectional, or 16-bit Bidirectional External Data Interface

■Synchronous Field and EOP Detection on Receive Packets

■Synchronous Field and EOP Generation on Transmit Packets

■Data and Clock Recovery from the USB Serial Stream

■Bit stuffing and unstuffing; Bit Stuff Error Detection

■Staging Register to manage Data Rate variation due to Bit stuffing and unstuffing

■16-bit 30 MHz and 8-bit 60 MHz Parallel Interface

■Ability to switch between FS and HS terminations and signaling

■Supports detection of USB Reset, Suspend, and Resume

■Supports HS identification and detection as defined by the USB 2.0 Specification

■Supports transmission of Resume Signaling

■3.3V Operation

■Two package options: 56-pin QFN and 56-pin VFBGA

■All required terminations, including 1.5 Kohm pull up on DPLUS, are internal to chip

■Supports USB 2.0 Test Modes

The Cypress MoBL-USB TX2 is a Universal Serial Bus (USB) specification revision 2.0 transceiver, serial and deserializer, to a parallel interface of either 16 bits at 30 MHz or eight bits at 60 MHz. The MoBL-USB TX2 provides a high speed physical layer interface that operates at the maximum allowable USB 2.0 bandwidth. This enables the system designer to keep the complex high speed analog USB components external to the digital ASIC. This decreases development time and associated risk. A standard USB 2.0-certified interface is provided and is compliant with Transceiver Macrocell Interface (UTMI) specifi- cation version 1.05 dated 3/29/2001.

This product is also optimized to seamlessly interface with Monahans -P & -L applications processors. It has been charac- terized by Intel and is recommended as the USB 2.0 UTMI trans- ceiver of choice for its Monahans processors. It is also capable of tri-stating the UTMI bus, while suspended, to enable the bus to be shared with other devices.

Two packages are defined for the family: 56-pin QFN and 56-pin

VFBGA.

The functional block diagram follows.

Logic Block Diagram

Tri_state

Cypress Semiconductor Corporation • 198 Champion Court	•	San Jose, CA 95134-1709	•	408-943-2600
Document #: 38-08052 Rev. *G		Revised October 5, 2008

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