Cypress CY7C68000A PCB Layout Recommendations, Vfbga 5 x 5 x 1.0 mm 0.50 Pitch, 0.30 Ball BZ56

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CY7C68000A

Package Diagrams (continued)

Figure 7. 56 VFBGA (5 x 5 x 1.0 mm) 0.50 Pitch, 0.30 Ball BZ56

TOP VIEW

 

 

PIN A1 CORNER

 

 

 

 

 

 

 

1

2

3

4

5

6

6

8

 

 

 

 

 

 

 

 

 

 

 

 

 

 

A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

B

 

 

 

 

 

 

 

5.00±0.10

C

 

 

 

 

 

 

 

D

 

 

 

 

 

 

 

E

 

 

 

 

 

 

 

F

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

G

 

 

 

 

 

 

 

BOTTOM VIEW

 

 

 

 

Ø0.05 M C

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ø0.15 M C A

B

 

 

 

 

A1 CORNER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Ø0.30±0.05(56X)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

8

7

6

5

4

3

2

1

 

 

 

 

 

 

 

 

 

A

 

 

0.50

 

 

 

 

 

 

B

5.00±0.10

3.50

 

 

 

 

 

 

C

 

 

 

 

 

 

D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E

 

 

 

 

 

 

 

 

 

F

 

 

 

 

 

 

 

 

 

G

H

5.00±0.10

-B-

-A-

H

0.50

3.50

5.00±0.10

 

SIDE VIEW

C

 

 

0.10

 

0.45

 

0.080 C

-C-

SEATING PLANE

 

 

0.21

 

~0.260

1.0 max

 

 

0.160

 

0.10(4X)

REFERENCE JEDEC: MO-195C

PACKAGE WEIGHT: 0.02 grams

001-03901-*B

PCB Layout Recommendations

Follow these recommendations to ensure reliable, high-perfor- mance operation[3].

A four-layer impedance controlled board is required to maintain signal quality

Specify impedance targets (ask your board vendor what they can achieve)

To control impedance, maintain trace widths and trace spacing to within written specifications

Minimize stubs to minimize reflected signals

Note

Connections between the USB connector shell and signal ground must be done near the USB connector

Bypass and flyback capacitors on VBus, near the connector, are recommended

Keep DPLUS and DMINUS trace lengths within 2 mm of each other in length, with preferred length of 20 to 30 mm

Maintain a solid ground plane under the DPLUS and DMINUS traces. Do not split the plane under these traces

Do not place vias on the DPLUS or DMINUS trace routing

Isolate the DPLUS and DMINUS traces from all other signal traces by no less than 10 mm

3.Source for recommendations: EZ-USB FX2™ PCB Design Recommendations, http:///www.cypress.com/cfuploads/support/app_notes/FX2_PCB.pdf High-Speed USB Platform Design Guidelines, http://www.usb.org/developers/docs/hs_usb_pdg_r1_0.pdf.

Document #: 38-08052 Rev. *G

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Contents Logic Block Diagram MoBL-USBTX2 FeaturesVfbga Cypress Semiconductor Corporation 198 Champion CourtFunctional Overview ApplicationsDPLUS/DMINUS Impedance Termination Operational ModesOpMode10 Description CY7C68000A Pin ConfigurationsCY7C68000A 56-pin Vfbga Pin Assignment Pin Descriptions Name Type Default Description1Pin Descriptions By the Transmit State Machine Xtalin Receive ErrorXtalout GNDAbsolute Maximum Ratings DC CharacteristicsOperating Conditions DPLUS/DMINUS/CLKTiming Diagram HS/FS Interface Timing 60 MHz AC Electrical CharacteristicsHS/FS Interface Timing 30 MHz Ordering Information Package DiagramsOrdering Code Package Type Vfbga 5 x 5 x 1.0 mm 0.50 Pitch, 0.30 Ball BZ56 PCB Layout RecommendationsCross section of the Area Underneath the QFN Package Quad Flat Package No Leads QFN Package Design NotesWorldwide Sales and Design Support Products PSoC Solutions Sales, Solutions, and Legal InformationDocument History Orig. Submission Description of Change Date