Cypress CY7C68000A Operational Modes, DPLUS/DMINUS Impedance Termination, OpMode10 Description

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CY7C68000A

Operational Modes

The operational modes are controlled by the OpMode signals. The OpMode signals are capable of inhibiting normal operation of the transceiver and evoking special test modes. These modes take effect immediately and take precedence over any pending data operations. The transmission data rate when in OpMode depends on the state of the XcvrSelect input.

OpMode[1:0]

Mode

Description

00

0

Normal operation

 

 

 

01

1

Non-driving

 

 

 

10

2

Disable Bit Stuffing and NRZI

 

 

encoding

11

3

Reserved

 

 

 

Mode 0 enables the transceiver to operate with normal USB data decoding and encoding.

Mode 1 enables the transceiver logic to support a soft disconnect feature that tri-states both the HS and FS transmitters, and removes any termination from the USB, making it appear to an upstream port that the device is disconnected from the bus.

Mode 2 disables Bit Stuff and NRZI encoding logic so ‘1’s loaded from the data bus becomes ‘J’s on the DPLUS/DMINUS lines and ‘0’s become ‘K’s.

DPLUS/DMINUS Impedance Termination

The CY7C68000A does not require external resistors for USB data line impedance termination or an external pull up resistor on the DPLUS line. These resistors are incorporated into the part. They are factory trimmed to meet the requirements of USB 2.0. Incorporating these resistors also reduces the pin count on the part.

Document #: 38-08052 Rev. *G

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Contents Cypress Semiconductor Corporation 198 Champion Court MoBL-USBTX2 FeaturesLogic Block Diagram VfbgaFunctional Overview ApplicationsOperational Modes DPLUS/DMINUS Impedance TerminationOpMode10 Description CY7C68000A Pin ConfigurationsCY7C68000A 56-pin Vfbga Pin Assignment Name Type Default Description1 Pin DescriptionsPin Descriptions By the Transmit State Machine GND Receive ErrorXtalin XtaloutDPLUS/DMINUS/CLK DC CharacteristicsAbsolute Maximum Ratings Operating ConditionsTiming Diagram HS/FS Interface Timing 60 MHz AC Electrical CharacteristicsHS/FS Interface Timing 30 MHz Package Diagrams Ordering InformationOrdering Code Package Type Vfbga 5 x 5 x 1.0 mm 0.50 Pitch, 0.30 Ball BZ56 PCB Layout RecommendationsCross section of the Area Underneath the QFN Package Quad Flat Package No Leads QFN Package Design NotesOrig. Submission Description of Change Date Sales, Solutions, and Legal InformationWorldwide Sales and Design Support Products PSoC Solutions Document History