Cypress CY62167EV18 Maximum Ratings, Operating Range, Electrical Characteristics, Capacitance

CY62167EV18 MoBL®

Maximum Ratings

Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested.

Storage Temperature	–65°C to + 150°C
Ambient Temperature with
Power Applied	–55°C to + 125°C
Supply Voltage to Ground
Potential	–0.2V to 2.45V (VCC(max) + 0.2V)
DC Voltage Applied to Outputs
in High Z State[6, 7]	–0.2V to 2.45V (VCC(max) + 0.2V)

DC Input Voltage[6, 7]		....... –0.2V to 2.45V (VCC(max) + 0.2V)
Output Current into Outputs (LOW)				20 mA
Static Discharge Voltage				>2001V
(MIL-STD-883, Method 3015)
Latch up Current				>200 mA
Operating Range
Device		Range	Ambient	[8]
			Temperature	VCC
CY62167EV18LL	Industrial		–40°C to +85°C	1.65V to 2.25V

Electrical Characteristics

Over the Operating Range

Parameter

Description

Test Conditions

55 ns

Unit

Min

Typ[4]

Max

VOH

Output HIGH Voltage

IOH = –0.1 mA

1.4

V

VOL

Output LOW Voltage

IOL = 0.1 mA

0.2

V

VIH

Input HIGH Voltage

VCC = 1.65V to 2.25V

1.4

VCC + 0.2V

V

VIL

Input LOW Voltage

VCC = 1.65V to 2.25V

–0.2

0.4

V

IIX

Input Leakage Current

GND < VI < VCC

–1

+1

μA

IOZ

Output Leakage Current

GND < VO < VCC, Output Disabled

–1

+1

μA

ICC

VCC Operating Supply

f = fmax = 1/tRC

VCC = VCC(max)

25

30

mA

Current

IOUT = 0 mA

f = 1 MHz

2.2

4.0

mA

CMOS levels

ISB1

Automatic CE Power Down

1 > VCC – 0.2V or CE2 < 0.2V

1.5

12

μA

CE

Current – CMOS Inputs

VIN > VCC – 0.2V, VIN < 0.2V)

f = fmax(Address and Data Only),

f = 0 (OE,

WE,

BHE

and

BLE),

VCC = VCC(max)

ISB2[9]

Automatic CE Power Down

1 > VCC – 0.2V or CE2 < 0.2V,

1.5

12

μA

CE

Current – CMOS Inputs

VIN > VCC – 0.2V or VIN < 0.2V,

f = 0, VCC = VCC(max)

Capacitance

Tested initially and after any design or process changes that may affect these parameters.

Parameter	Description	Test Conditions	Max	Unit
CIN	Input Capacitance	TA = 25°C, f = 1 MHz,	10	pF
		VCC = VCC(typ)
COUT	Output Capacitance		10	pF

Notes

6.VIL(min) = –2.0V for pulse durations less than 20 ns.

7.VIH(max) = VCC + 0.75V for pulse durations less than 20 ns.

8.Full Device AC operation is based on a 100 μs ramp time from 0 to VCC(min) and 200 μs wait time after VCC stabilization.

9.Only chip enables (CE1 and CE2), and byte enables (BHE and BLE) must be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating.

Document #: 38-05447 Rev. *G Page 3 of 13

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