Cypress CY62167EV18 manual Shows WE controlled write cycle waveforms.17, 21, Data I/O Valid Data

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CY62167EV18 MoBL®

Switching Waveforms (continued)

Figure 6 shows WE controlled write cycle waveforms.[17, 21, 22]

Figure 6. Write Cycle No. 1

 

 

tWC

ADDRESS

 

 

 

 

tSCE

CE1

 

 

CE2

 

 

 

tAW

tHA

WE

tSA

tPWE

 

 

BHE/BLE

 

tBW

 

 

OE

 

tHD

 

 

tSD

DATA I/O

NOTE 23

VALID DATA

 

tHZOE

 

Notes

21.Data IO is high impedance if OE = VIH.

22.If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.

23.During this period the IOs are in output state. Do not apply input signals.

Document #: 38-05447 Rev. *G

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Contents Cypress Semiconductor Corporation 198 Champion Court FeaturesLogic Block Diagram Functional DescriptionBLE BHE Pin ConfigurationProduct Portfolio Min Typ Max CY62167EV18LL CY62167EV30LLCapacitance Electrical CharacteristicsMaximum Ratings Operating RangeThermal Resistance Data Retention CharacteristicsVfbga Parameter Description 55 ns Unit Min Max Read Cycle Switching Waveforms Data I/O Valid Data Shows WE controlled write cycle waveforms.17, 21Shows CE1 or CE2 controlled write cycle waveforms.17, 21 Truth Table Inputs/Outputs Mode PowerCE1 CE2 BHE BLE Ordering Information Package DiagramBall Vfbga 6 x 8 x 1 mm REV ECN no Document HistoryOrig. Submission Change Date Description of Change USB Sales, Solutions, and Legal Information