Cypress CY62167EV18 manual Shows CE1 or CE2 controlled write cycle waveforms.17, 21

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CY62167EV18 MoBL®

Switching Waveforms (continued)

Figure 7 shows CE1 or CE2 controlled write cycle waveforms.[17, 21, 22]

Figure 7. Write Cycle No. 2

 

 

tWC

ADDRESS

 

 

 

 

tSCE

CE1

 

 

CE2

 

 

 

tSA

tHA

 

tAW

WE

 

tPWE

 

 

BHE/BLE

 

tBW

 

 

OE

 

tHD

 

 

tSD

DATA I/O

NOTE 23

VALID DATA

 

tHZOE

 

Figure 8 shows WE controlled, OE LOW write cycle waveforms.[22]

Figure 8. Write Cycle No. 3

 

 

tWC

 

ADDRESS

 

 

 

 

 

tSCE

 

CE1

 

 

 

CE2

 

 

 

BHE/BLE

 

tBW

 

 

 

 

 

tAW

 

tHA

WE

tSA

tPWE

 

 

 

 

 

 

tSD

tHD

DATA I/O

NOTE 23

VALID DATA

 

 

tHZWE

 

tLZWE

Document #: 38-05447 Rev. *G

 

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Contents Features Logic Block DiagramFunctional Description Cypress Semiconductor Corporation 198 Champion CourtPin Configuration Product PortfolioMin Typ Max CY62167EV18LL CY62167EV30LL BLE BHEElectrical Characteristics Maximum RatingsOperating Range CapacitanceVfbga Data Retention CharacteristicsThermal Resistance Parameter Description 55 ns Unit Min Max Read Cycle Switching Waveforms Shows WE controlled write cycle waveforms.17, 21 Data I/O Valid DataShows CE1 or CE2 controlled write cycle waveforms.17, 21 CE1 CE2 BHE BLE Inputs/Outputs Mode PowerTruth Table Package Diagram Ordering InformationBall Vfbga 6 x 8 x 1 mm Orig. Submission Change Date Description of Change Document HistoryREV ECN no Sales, Solutions, and Legal Information USB