Cypress CY62167EV18 manual Parameter Description 55 ns Unit Min Max Read Cycle

						CY62167EV18 MoBL®
Switching Characteristics
Over the Operating Range[13, 14]
Parameter				Description		55 ns		Unit
					Min		Max
Read Cycle
tRC	Read Cycle Time				55			ns
tAA	Address to Data Valid						55	ns
tOHA	Data Hold from Address Change				10			ns
tACE		1 LOW and CE2 HIGH to Data Valid					55	ns
	CE
tDOE			LOW to Data Valid				25	ns
	OE
tLZOE			LOW to Low-Z[15]		5			ns
	OE
tHZOE			HIGH to High-Z[15, 16]				18	ns
	OE
tLZCE		1 LOW and CE2 HIGH to Low-Z[15]			10			ns
	CE
tHZCE		1 HIGH and CE2 LOW to High-Z[15, 16]					18	ns
	CE
tPU		1 LOW and CE2 HIGH to Power Up			0			ns
	CE
tPD		1 HIGH and CE2 LOW to Power Down					55	ns
	CE
tDBE	BLE/BHE LOW to Data Valid						55	ns
tLZBE					10			ns
	BLE/BHE LOW to Low-Z[15]
tHZBE							18	ns
	BLE/BHE HIGH to High-Z[15,16]
Write Cycle[17]
tWC	Write Cycle Time				55			ns
tSCE		1 LOW and CE2 HIGH to Write End			40			ns
	CE
tAW	Address Setup to Write End				40			ns
tHA	Address Hold from Write End				0			ns
tSA	Address Setup to Write Start				0			ns
tPWE			Pulse Width		40			ns
	WE
tBW					40			ns
	BLE/BHE LOW to Write End
tSD	Data Setup to Write End				25			ns
tHD	Data Hold from Write End				0			ns
tHZWE			LOW to High-Z[15, 16]				20	ns
	WE
tLZWE			HIGH to Low-Z[15]		10			ns
	WE

Notes

13.Test conditions for all parameters other than tri-state parameters are based on signal transition time of 1V/ns, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in AC Test Loads and Waveforms on page 4.

14.AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification.

15.At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.

16.tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the output enters a high impedance state.

17.The internal memory write time is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.

Document #: 38-05447 Rev. *G Page 5 of 13

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