Cypress CY62146EV30 manual Features, Functional Description, Product Portfolio

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Features

Very high speed: 45 ns

Wide voltage range: 2.20V–3.60V

Pin compatible with CY62146DV30

Ultra low standby power

— Typical standby current: 1 A

CY62146EV30 MoBL®

4-Mbit (256K x 16) Static RAM

reduces power consumption by 80% when addresses are not toggling. The device can also be put into standby mode reducing power consumption by more than 99% when deselected (CE HIGH). The input and output pins (IO0 through IO15) are placed in a high impedance state when:

Deselected (CE HIGH)

Outputs are disabled (OE HIGH)

Maximum standby current: 7 A

Ultra low active power

Typical active current: 2 mA @ f = 1 MHz

Easy memory expansion with CE, and OE features

Automatic power down when deselected

CMOS for optimum speed and power

Available in a Pb-free 48-ball VFBGA and 44-pin TSOP II packages

Both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH)

Write operation is active (CE LOW and WE LOW)

Write to the device by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7), is written into the location specified on the address pins (A0 through A17). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A17).

Functional Description [1]

The CY62146EV30 is a high performance CMOS static RAM organized as 256K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly

Read from the device by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on IO0 to IO7. If

Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See the “Truth Table” on page 9 for a complete description of read and write modes.

Product Portfolio

 

 

 

 

 

 

 

 

 

 

Power Dissipation

 

 

 

 

 

 

 

 

Speed

 

 

 

 

 

 

 

 

 

Product

 

VCC Range (V)

 

 

Operating ICC (mA)

 

 

 

 

 

 

(ns)

 

 

 

Standby ISB2 (A)

 

 

 

 

 

 

 

f = 1 MHz

f = fmax

 

 

 

 

 

 

 

 

 

 

 

 

Min

 

Typ [2]

 

Max

 

Typ [2]

 

Max

Typ [2]

 

Max

 

Typ [2]

Max

CY62146EV30LL

2.2

 

3.0

 

3.6

45 ns

2

 

2.5

15

 

20

 

1

7

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Notes:

1.For best practice recommendations, please refer to the Cypress application note System Design Guidelines on http://www.cypress.com.

2.Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C.

Cypress Semiconductor Corporation

• 198 Champion Court

• San Jose, CA 95134-1709

408-943-2600

Document #: 38-05567 Rev. *C

 

Revised March 26, 2007

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Contents Functional Description FeaturesProduct Portfolio Pin Configurations 3 Logic Block DiagramBall Vfbga Pin Tsop Top ViewMaximum Ratings Electrical Characteristics Over the Operating RangeOperating Range Thermal Resistance Data Retention Characteristics Over the Operating RangeAC Test Loads and Waveforms Data Retention WaveformWrite Cycle 45 ns Parameter Description Min Max Unit Read CycleAddress Switching WaveformsData OUT Previous Data Valid Write Cycle No CE Controlled 15, 19 Write Cycle No WE Controlled 15, 19Write Cycle No WE Controlled, OE LOW Truth Table Inputs/Outputs Mode PowerOrdering Information BHE BLEBall Vfbga 6 x 8 x 1 mm Package DiagramsPin Tsop II Document History Issue Date Orig. Description of ChangeREV ECN no