Cypress CY62146EV30 manual Document History, REV ECN no, Issue Date Orig. Description of Change

Page 12

CY62146EV30 MoBL®

Document History Page

Document Title:CY62146EV30 MoBL®, 4-Mbit (256K x 16) Static RAM

Document Number: 38-05567

REV.

ECN NO.

Issue Date

Orig. of

Description of Change

Change

 

 

 

 

 

**

223225

See ECN

AJU

New Data Sheet

 

 

 

 

 

*A

247373

See ECN

SYT

Changed Advance Information to Preliminary

 

 

 

 

Moved Product Portfolio to Page 2

 

 

 

 

Changed VCC stabilization time in footnote #8 from 100 s to 200 s

 

 

 

 

Removed Footnote #14(tLZBE) from Previous revision

 

 

 

 

Changed ICCDR from 2.0 A to 2.5 A

 

 

 

 

Changed typo in Data Retention Characteristics(tR) from 100 s to tRC ns

 

 

 

 

Changed tOHA from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin

 

 

 

 

Changed tHZOE, tHZBE, tHZWE from 12 to 15 ns for 35 ns Speed Bin and 15 to

 

 

 

 

18 ns for 45 ns Speed Bin

 

 

 

 

Changed tSCE and tBW from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns

 

 

 

 

for 45 ns Speed Bin

 

 

 

 

Changed tHZCE from 12 to 18 ns for 35 ns Speed Bin and 15 to 22 ns for 45

 

 

 

 

ns Speed Bin

 

 

 

 

Changed tSD from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for

 

 

 

 

45 ns Speed Bin

 

 

 

 

Changed tDOE from 15 to 18 ns for 35 ns Speed Bin

 

 

 

 

Changed tDBE from 15 to 18 ns for 35 ns Speed Bin

 

 

 

 

Changed Ordering Information to include Pb-Free Packages

*B

414807

See ECN

ZSD

Changed from Preliminary information to Final

 

 

 

 

Changed the address of Cypress Semiconductor Corporation on Page #1

 

 

 

 

from “3901 North First Street” to “198 Champion Court”

 

 

 

 

Removed 35ns Speed Bin

 

 

 

 

Removed “L” version of CY62146EV30

 

 

 

 

Changed ball E3 from DNU to NC

 

 

 

 

Removed the redundant foot note on DNU.

 

 

 

 

Changed ICC (Max) value from 2 mA to 2.5 mA and ICC (Typ) value from

 

 

 

 

1.5 mA to 2 mA at f=1 MHz

 

 

 

 

Changed ICC (Typ) value from 12 mA to 15 mA at f = fmax

 

 

 

 

Changed ISB1 and ISB2 Typ values from 0.7 A to 1 A and Max values from

 

 

 

 

2.5 A to 7 A.

 

 

 

 

Changed the AC test load capacitance from 50pF to 30pF on Page# 4

 

 

 

 

Changed ICCDR from 2.5 A to 7 A.

 

 

 

 

Added ICCDR typical value.

 

 

 

 

Changed tLZOE from 3 ns to 5 ns

 

 

 

 

Changed tLZCE and tLZWE from 6 ns to 10 ns

 

 

 

 

Changed tLZBE from 6 ns to 5 ns

 

 

 

 

Changed tHZCE from 22 ns to 18 ns

 

 

 

 

Changed tPWE from 30 ns to 35 ns.

 

 

 

 

Changed tSD from 22 ns to 25 ns.

 

 

 

 

Updated the package diagram 48-ball VFBGA from *B to *D

 

 

 

 

Updated the ordering information table and replaced the Package Name

 

 

 

 

column with Package Diagram.

*C

925501

See ECN

VKN

Added footnote #8 related to ISB2 and ICCDR

 

 

 

 

Added footnote #12 related AC timing parameters

Document #: 38-05567 Rev. *C

Page 12 of 12

Image 12
Contents Features Functional DescriptionProduct Portfolio Logic Block Diagram Pin Configurations 3Ball Vfbga Pin Tsop Top ViewElectrical Characteristics Over the Operating Range Maximum RatingsOperating Range Data Retention Characteristics Over the Operating Range Thermal ResistanceAC Test Loads and Waveforms Data Retention Waveform45 ns Parameter Description Min Max Unit Read Cycle Write CycleSwitching Waveforms AddressData OUT Previous Data Valid Write Cycle No WE Controlled 15, 19 Write Cycle No CE Controlled 15, 19Write Cycle No WE Controlled, OE LOW Inputs/Outputs Mode Power Truth TableOrdering Information BHE BLEPackage Diagrams Ball Vfbga 6 x 8 x 1 mmPin Tsop II Issue Date Orig. Description of Change Document HistoryREV ECN no