The MSTR Instruction
3.2.12Write CTE (Config Extension Table) MSTR Operation
The Write CTE operation (type 12 in the displayed register of the top node) reads an indicated number of bytes from PLC memory, starting at a specified byte address, to an indicated Ethernet configuration extension table at a specified offset. The content of the Ethernet CTE table is displayed in the middle node of the MSTR block.
Control Block | The registers in the MSTR control block (the top node) contain the Write CTE | ||||||
Utilization | information as described in the following table: | ||||||
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| Register | Function | Content |
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| Displayed | Operation Type | 12 |
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| First implied | Error status | Displays a hex value indicating an MSTR error, |
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| Second implied | Not applicable |
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| Third implied | Not applicable |
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| Fourth implied | Low byte | Quantum backplane slot address of the NOE |
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| Fifth ... Eight | Not applicable |
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| implied |
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CTE Display |
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The values in the Ethernet configuration extension table (CTE) are displayed in a | |||||||
Implementation | series of registers in the middle node of the MSTR instruction when a Write CTE | ||||||
| operation is implemented. The middle node contains the first of 11 contiguous 4x | ||||||
| registers. The registers display the following CTE data: | ||||||
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| Parameter |
| Register |
| Content |
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| Frame type |
| Displayed |
| 1 = 802.3 |
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| 2 = Ethernet |
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| IP Address |
| First implied |
| First byte of the IP address |
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| Second implied | Second byte of the IP address |
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| Third implied |
| Third byte of the IP address |
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| Fourth implied |
| Fourth byte of the IP address |
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| Subnetwork mask | Fifth implied |
| Hi word |
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| Sixth implied |
| Low word |
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| Gateway |
| Seventh implied | First byte of the gateway |
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| Eighth implied |
| Second byte of the gateway |
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| Ninth implied |
| Third byte of the gateway |
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| Tenth implied |
| Fourth byte of the gateway |
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840 USE 115 00 Version 1.0 | 39 |