Transcend Information TS2G-8GCF266 manual TS2G~8GCF266266X CompactFlash Card

Page 14
￿ Additional Requirements for CF Advanced Timing Modes

TS2G~8GCF266266X CompactFlash Card

Notes: 1) Control Signals: each card shall present a load to the socket no larger than 50 pF 10 at a DC current of 700 A low state and 150 A high state, including pull-resistor. The socket shall be able to drive at least the following

10 while meeting all AC timing requirements: 50 pF at a DC current of 400 A low state and 100 A high state.μ 4) Status Signals: the socket shall present a load to the card no larger than 50 pF 10 at a DC current of 400 A low

state and 100 A μhigh state, including pull-up resistor. The card shall be able to drive at least the following load 10 while meeting all AC timing requirements: 50 pF at a DC current of 400 A low state and 100 A high state.

load 10 while meeting all AC timing requirements: (the number of sockets wired in parallel) multiplied by (50 pF

with DC current 700 A low state and 150 A high state per socket). 2) Resistor is optional.

3) Status Signals: the socket shall present a load to the card no larger than 50 pF 10 at a DC current of 400 A low

state and 100 A high state, including pull-up resistor. The card shall be able to drive at least the following load

5) Status Signals: the socket shall present a load to the card no larger than 50 pF 10 at a DC current of 400 A low

μ

μ

state and 100 A high state, including pull-up resistor. The card shall be able to drive at least the following load

10 while meeting all AC timing requirements: 50 pF at a DC current of 400

 

A low state and 1100

 

μ

 

 

A high state.

6) BVD2 was not definedμ

in the JEIDA 3.0 release. Systems fully supporting JEIDA release 3 SRAM cards shall

pull-up pin 45 (BVD2) to avoid sensing their batteries as “Low.”

μ

 

μ

 

 

 

 

 

7) Address Signals: each card shall present a load of no more than 100pF 10 at a DC current of 450

A low state and

 

 

 

 

 

μ

150 A high state. The host shall be able to drive at least the following load 10 while meeting all AC timing

μ

 

 

 

 

 

requirements: (the number of sockets wired in parallel) multiplied by (100pF with DC current 450 A low state

and 150 A high state per socket).

μ

 

μ

 

8) Data Signals: the host and each card shall present a load no larger than 50pF 10 at a DC current of 450 μ A and

μ

 

 

 

 

 

150 A high state. The host and each card shall be able to drive at least the following load 10 while meeting all

AC timing requirements: 100pF with DC current 1.6mA low state and 300

μ

 

μ

 

 

A high state. This permits the host to

9) Resetμ Signal:μ This signal is pulled up to prevent the input from floating when a CFA to PCMCIAμ adapterμ is used in a PCMCIA revision 1 host. However, to minimize DC current drain through the pull-up resistor in normal operation the pull-up should be turned off once the Reset signal has been actively driven low by the host. Consequently, the input is specified as an I2Z because the resistor is not necessarily detectable in the input current leakage test.

wire two sockets in parallel without derating the card access speeds.

10) Host and card restrictions for CF Advanced Timing Modes and Ultra DMA modes: Additional Requirements for

CF Advancedμ Timing Modes and Ultra DMA Electrical Requirements forμadditional required limitations μon the implementation of CF Advanced Timing modes and Ultra DMA modes respectively.

The CF Advanced Timing modes include PCMCIA I/O and Memory modes that are 100ns or faster and True IDE PIO Modes 5,6 and Multiword DMA Modes 3,4.

When operating in CF Advanced timing modes, the host shall conform to the following requirements:

1)Only one CF device shall be attached to the CF Bus.

2)The host shall not present a load of more than 40pF to the device for all signals, including any cabling.

3)The maximum cable length is 0.15 m (6 in). The cable length is measured from the card connector to the host controller. 0.46 m (18 in) cables are not supported.

4)The -WAIT and IORDY signals shall be ignored by the host.

Devices supporting CF Advanced timing modes shall also support slower timing modes, to ensure operability with systems that do not support CF Advanced timing modes

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Contents Description Placement FeaturesDimensions Transcend Block Diagram Pin Assignments and Pin Type TS2G~8GCF266 Signal Description TS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 Electrical Specification Output Drive Type Output Drive Characteristics Signal Interface TS2G~8GCF266266X CompactFlash Card Pull-up pin 45 BVD2 to avoid sensing their batteries as LowTable Typical Series Termination for Ultra DMA Ultra DMA Electrical RequirementsSeries termination required for Ultra DMA operation Ultra DMA Mode Cabling Requirement Attribute Memory Read Timing Specification TS2G~8GCF266 Common Memory Read Timing Specification Common Memory Write Timing Specification Input Read Timing Specification TS2G~8GCF266 Output Write Timing Specification TS2G~8GCF266 True IDE PIO Mode Read/Write Timing Specification TS2G~8GCF266 True IDE Ultra DMA Mode Read/Write Timing Specification Table Ultra DMA Data Burst TimingTS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 Multiple Function CF+ Cards Card ConfigurationSingle Function CF+ Cards Table CF+ Card Configuration Registers Decoding Table CF+ Card Register and Memory Space DecodingAttribute Memory Function Attribute Memory FunctionConfiguration Option Register Base + 00h in Attribute Memory TS2G~8GCF266 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory Table Pcmcia Mode I/O Function Transfer FunctionCommon Memory Transfer Function Table Common Memory FunctionTrue IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Primary and Secondary Address Configurations Table Primary and Secondary I/O DecodingContiguous I/O Mapped Addressing Table Contiguous I/O DecodingTrue IDE Mode Addressing Memory Mapped AddressingCF-ATA Registers Data Register Address 1F0h170hOffset 0,8,9Sector Number LBA 7-0 Register Address 1F3h173h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Count Register Address 1F2h172h Offset Cylinder Low LBA 15-8 Register Address 1F4h174h OffsetTS2G~8GCF266 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh CF-ATA Command Set Check Power Mode 98h or E5h Execute Drive Diagnostic 90h Erase Sectors C0hFlush Cache E7h Format Track 50hIdentify Device Ech TS2G~8GCF266 Word 0 General Configuration Word 6 Default Number of Sectors per Track Word 1 Default Number of CylindersWord 3 Default Number of Heads Word 49 Capabilities Bit 13 Standby TimerTranslation Parameters Valid Multiple Sector SettingTotal Sectors Addressable in LBA Mode Current Number of Cylinders, Heads, Sectors/TrackRecommended Multiword DMA transfer cycle time Words 82-84 Features/command sets supportedWord 65 Minimum Multiword DMA transfer cycle time Word 68 Minimum PIO transfer cycle time with IordyWords 85-87 Features/command sets enabled Word 88 Ultra DMA Modes Supported and Selected Word 89 Time required for Security erase unit completionWord 128 Security Status Bit 8 Security Level Word 91 Advanced power management level valueWord 160 Power Requirement Description Additional Requirements for CF Advanced Timing ModesTS2G~8GCF266 Idle 97h or E3h NOP 00h Idle Immediate 95h or E1hInitialize Drive Parameters 91h Read Buffer E4h Read DMA C8h Read Long Sector 22h or 23hTS2G~8GCF266 Recalibrate 1Xh Request Sense 03h Seek 7Xh Set Features EFh Feature Supported TS2G~8GCF266 Standby Immediate 94h or E0h Translate Sector 87h Translate Sector InformationWear Level F5h Write Buffer E8h Write DMA CAh TS2G~8GCF266 TS2G~8GCF266 Error Posting S. Table Capacity Smart Command SetSmart Command Set Smart Feature Register Values Smart Data Structure Decription
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