Transcend Information TS2G-8GCF266 manual Device Control Register Address 3F6h376h Offset Eh

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TS2G~8GCF266		266X CompactFlash Card

Device Control Register (Address - 3F6h[376h]; Offset Eh)

This register is used to control the CompactFlash Storage Card interrupt request and to issue an ATA soft reset to the card. This register can be written even if the device is BUSY. The bits are defined as follows:

Bit 7: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 6: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 5: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 4: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 3: this bit is ignored by the CompactFlash Storage Card. The host software should set this bit to 0.

Bit 2 (SW Rst): this bit is set to 1 in order to force the CompactFlash Storage Card to perform an AT Disk controller Soft Reset operation. This does not change the PCMCIA Card Configuration Registers as a hardware Reset does. The Card remains in Reset until this bit is reset to ‘0.’

Bit 1 (-IEn): the Interrupt Enable bit enables interrupts when the bit is 0. When the bit is 1, interrupts from the CompactFlash Storage Card are disabled. This bit also controls the Int bit in the Configuration and Status Register. This bit is set to 0 at power on and Reset.

Bit 0: this bit is ignored by the CompactFlash Storage Card.

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Contents Description Placement FeaturesDimensions Transcend Block Diagram Pin Assignments and Pin Type TS2G~8GCF266 Signal Description TS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 Electrical Specification Output Drive Type Output Drive Characteristics Signal Interface TS2G~8GCF266266X CompactFlash Card Pull-up pin 45 BVD2 to avoid sensing their batteries as LowTable Typical Series Termination for Ultra DMA Ultra DMA Electrical RequirementsSeries termination required for Ultra DMA operation Ultra DMA Mode Cabling Requirement Attribute Memory Read Timing Specification TS2G~8GCF266 Common Memory Read Timing Specification Common Memory Write Timing Specification Input Read Timing Specification TS2G~8GCF266 Output Write Timing Specification TS2G~8GCF266 True IDE PIO Mode Read/Write Timing Specification TS2G~8GCF266 True IDE Ultra DMA Mode Read/Write Timing Specification Table Ultra DMA Data Burst TimingTS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 Multiple Function CF+ Cards Card ConfigurationSingle Function CF+ Cards Table CF+ Card Configuration Registers Decoding Table CF+ Card Register and Memory Space DecodingAttribute Memory Function Attribute Memory FunctionConfiguration Option Register Base + 00h in Attribute Memory TS2G~8GCF266 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory Table Pcmcia Mode I/O Function Transfer FunctionCommon Memory Transfer Function Table Common Memory FunctionTrue IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Primary and Secondary Address Configurations Table Primary and Secondary I/O DecodingContiguous I/O Mapped Addressing Table Contiguous I/O DecodingTrue IDE Mode Addressing Memory Mapped AddressingCF-ATA Registers Data Register Address 1F0h170hOffset 0,8,9Sector Number LBA 7-0 Register Address 1F3h173h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Count Register Address 1F2h172h Offset Cylinder Low LBA 15-8 Register Address 1F4h174h OffsetTS2G~8GCF266 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh CF-ATA Command Set Check Power Mode 98h or E5h Execute Drive Diagnostic 90h Erase Sectors C0hFlush Cache E7h Format Track 50hIdentify Device Ech TS2G~8GCF266 Word 0 General Configuration Word 6 Default Number of Sectors per Track Word 1 Default Number of CylindersWord 3 Default Number of Heads Word 49 Capabilities Bit 13 Standby TimerTranslation Parameters Valid Multiple Sector SettingTotal Sectors Addressable in LBA Mode Current Number of Cylinders, Heads, Sectors/TrackRecommended Multiword DMA transfer cycle time Words 82-84 Features/command sets supportedWord 65 Minimum Multiword DMA transfer cycle time Word 68 Minimum PIO transfer cycle time with IordyWords 85-87 Features/command sets enabled Word 88 Ultra DMA Modes Supported and Selected Word 89 Time required for Security erase unit completionWord 128 Security Status Bit 8 Security Level Word 91 Advanced power management level valueWord 160 Power Requirement Description Additional Requirements for CF Advanced Timing ModesTS2G~8GCF266 Idle 97h or E3h NOP 00h Idle Immediate 95h or E1hInitialize Drive Parameters 91h Read Buffer E4h Read DMA C8h Read Long Sector 22h or 23hTS2G~8GCF266 Recalibrate 1Xh Request Sense 03h Seek 7Xh Set Features EFh Feature Supported TS2G~8GCF266 Standby Immediate 94h or E0h Translate Sector 87h Translate Sector InformationWear Level F5h Write Buffer E8h Write DMA CAh TS2G~8GCF266 TS2G~8GCF266 Error Posting S. Table Capacity Smart Command SetSmart Command Set Smart Feature Register Values Smart Data Structure Decription