Transcend Information TS2G-8GCF266 manual TS2G~8GCF266

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TS2G~8GCF266		266X CompactFlash Card

Data-In Burst Host Termination Timing), and tLI indicate sender-to-recipient or recipient-to-sender interlocks, i.e., one agent (either sender or recipient) is waiting for the other agent to respond with a signal before proceeding. tUI is an unlimited interlock that has no maximum time value. tMLI is a limited time-out that has a defined minimum. tLI is a limited time-out that has a defined maximum.

2)80-conductor cabling shall be required in order to meet setup (tDS, tCS) and hold (tDH, tCH) times in modes greater than 2.

3)Timing for tDVS, tDVH, tCVS and tCVH shall be met for lumped capacitive loads of 15 and 40 pF at the connector where the Data and STROBE signals have the same capacitive load value. Due to reflections on the cable, these timing measurements are not valid in a normally functioning system. 4)For all modes the parameter tZIORDY may be greater than tENV due to the fact that the host has a pull-up on IORDY- giving it a known state when released.

5)The parameters tDS, and tDH for mode 5 are defined for a recipient at the end of the cable only in a configuration with a single device located at the end of the cable. This could result in the minimum values for tDS and tDH for mode 5 at the middle connector being 3.0 and 3.9 ns respectively.

Notes: 1) All timing measurement switching points(low to high and high to low) shall be taken at 1.5 V.

2)The correct data value shall be captured by the recipient given input data with a slew rate of 0.4 V/ns rising and falling and the input STROBE with a slew rate of 0.4 V/ns rising and falling at tDSIC and tDHIC timing (as measured through 1.5 V).

3)The parameters tDVSIC and tDVHIC shall be met for lumped capacitive loads of 15 and 40 pF at the IC where all signals have the same capacitive load value. Noise that may couple onto the output signals from external sources has not been included in these values.

Transcend Information Inc.

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Contents Placement Features DimensionsDescription Transcend Block Diagram Pin Assignments and Pin Type TS2G~8GCF266 Signal Description TS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 Electrical Specification Output Drive Type Output Drive Characteristics Signal Interface TS2G~8GCF266266X CompactFlash Card Pull-up pin 45 BVD2 to avoid sensing their batteries as LowUltra DMA Electrical Requirements Series termination required for Ultra DMA operationTable Typical Series Termination for Ultra DMA Ultra DMA Mode Cabling Requirement Attribute Memory Read Timing Specification TS2G~8GCF266 Common Memory Read Timing Specification Common Memory Write Timing Specification Input Read Timing Specification TS2G~8GCF266 Output Write Timing Specification TS2G~8GCF266 True IDE PIO Mode Read/Write Timing Specification TS2G~8GCF266 True IDE Ultra DMA Mode Read/Write Timing Specification Table Ultra DMA Data Burst TimingTS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 Card Configuration Single Function CF+ CardsMultiple Function CF+ Cards Table CF+ Card Configuration Registers Decoding Table CF+ Card Register and Memory Space DecodingAttribute Memory Function Attribute Memory FunctionConfiguration Option Register Base + 00h in Attribute Memory TS2G~8GCF266 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory Table Pcmcia Mode I/O Function Transfer FunctionCommon Memory Transfer Function Table Common Memory FunctionTrue IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Primary and Secondary Address Configurations Table Primary and Secondary I/O DecodingContiguous I/O Mapped Addressing Table Contiguous I/O DecodingTrue IDE Mode Addressing Memory Mapped AddressingCF-ATA Registers Data Register Address 1F0h170hOffset 0,8,9Sector Number LBA 7-0 Register Address 1F3h173h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Count Register Address 1F2h172h Offset Cylinder Low LBA 15-8 Register Address 1F4h174h OffsetTS2G~8GCF266 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh CF-ATA Command Set Check Power Mode 98h or E5h Execute Drive Diagnostic 90h Erase Sectors C0hFlush Cache E7h Format Track 50hIdentify Device Ech TS2G~8GCF266 Word 0 General Configuration Word 6 Default Number of Sectors per Track Word 1 Default Number of CylindersWord 3 Default Number of Heads Word 49 Capabilities Bit 13 Standby TimerTranslation Parameters Valid Multiple Sector SettingTotal Sectors Addressable in LBA Mode Current Number of Cylinders, Heads, Sectors/TrackRecommended Multiword DMA transfer cycle time Words 82-84 Features/command sets supportedWord 65 Minimum Multiword DMA transfer cycle time Word 68 Minimum PIO transfer cycle time with IordyWords 85-87 Features/command sets enabled Word 88 Ultra DMA Modes Supported and Selected Word 89 Time required for Security erase unit completionWord 128 Security Status Bit 8 Security Level Word 91 Advanced power management level valueWord 160 Power Requirement Description Additional Requirements for CF Advanced Timing ModesTS2G~8GCF266 Idle 97h or E3h Idle Immediate 95h or E1h Initialize Drive Parameters 91hNOP 00h Read Buffer E4h Read DMA C8h Read Long Sector 22h or 23hTS2G~8GCF266 Recalibrate 1Xh Request Sense 03h Seek 7Xh Set Features EFh Feature Supported TS2G~8GCF266 Standby Immediate 94h or E0h Translate Sector 87h Translate Sector InformationWear Level F5h Write Buffer E8h Write DMA CAh TS2G~8GCF266 TS2G~8GCF266 Error Posting Smart Command Set Smart Command Set Smart Feature Register ValuesS. Table Capacity Smart Data Structure Decription