Transcend Information TS2G-8GCF266 manual TS2G~8GCF266

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TS2G~8GCF266		266X CompactFlash Card

Note: 1) These signals are required only for 16 bit accesses and not required when installed in 8 bit systems. Devices should allow for 3-state signals not to consume current.

2)The signal should be grounded by the host.

3)The signal should be tied to VCC by the host.

4)The mode is optional for CF+ Cards, but required for CompactFlash Storage Cards.

5)The -CSEL signal is ignored by the card in PC Card modes. However, because it is not pulled upon the card in these modes, it should not be left floating by the host in PC Card modes. In these modes, the pin should be connected by the host to PC Card A25 or grounded by the host.

6)If DMA operations are not used, the signal should be held high or tied to VCC by the host. For proper operation in older hosts: while DMA operations are not active, the card shall ignore this signal,including a floating condition

7)Signal usage in True IDE Mode except when Ultra DMA mode protocol is active.

8)Signal usage in True IDE Mode when Ultra DMA mode protocol DMA Write is active.

9)Signal usage in True IDE Mode when Ultra DMA mode protocol DMA Read is active.

10)Signal usage in PC Card I/O and Memory Mode when Ultra DMA mode protocol DMA Write is active.

11)Signal usage in PC Card I/O and Memory Mode when Ultra DMA mode protocol DMA Read is active.

12)Signal usage in PC Card I/O and Memory Mode when Ultra DMA protocol is active.

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Contents Description Placement FeaturesDimensions Transcend Block Diagram Pin Assignments and Pin Type TS2G~8GCF266 Signal Description TS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 Electrical Specification Output Drive Type Output Drive Characteristics Signal Interface Pull-up pin 45 BVD2 to avoid sensing their batteries as Low TS2G~8GCF266266X CompactFlash CardTable Typical Series Termination for Ultra DMA Ultra DMA Electrical RequirementsSeries termination required for Ultra DMA operation Ultra DMA Mode Cabling Requirement Attribute Memory Read Timing Specification TS2G~8GCF266 Common Memory Read Timing Specification Common Memory Write Timing Specification Input Read Timing Specification TS2G~8GCF266 Output Write Timing Specification TS2G~8GCF266 True IDE PIO Mode Read/Write Timing Specification TS2G~8GCF266 Table Ultra DMA Data Burst Timing True IDE Ultra DMA Mode Read/Write Timing SpecificationTS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 TS2G~8GCF266 Multiple Function CF+ Cards Card ConfigurationSingle Function CF+ Cards Table CF+ Card Register and Memory Space Decoding Table CF+ Card Configuration Registers DecodingAttribute Memory Function Attribute Memory FunctionConfiguration Option Register Base + 00h in Attribute Memory TS2G~8GCF266 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory Transfer Function Table Pcmcia Mode I/O FunctionTable Common Memory Function Common Memory Transfer FunctionTrue IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Table Primary and Secondary I/O Decoding Primary and Secondary Address ConfigurationsTable Contiguous I/O Decoding Contiguous I/O Mapped AddressingMemory Mapped Addressing True IDE Mode AddressingData Register Address 1F0h170hOffset 0,8,9 CF-ATA RegistersSector Count Register Address 1F2h172h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Number LBA 7-0 Register Address 1F3h173h Offset Cylinder Low LBA 15-8 Register Address 1F4h174h OffsetTS2G~8GCF266 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh CF-ATA Command Set Check Power Mode 98h or E5h Erase Sectors C0h Execute Drive Diagnostic 90hFormat Track 50h Flush Cache E7hIdentify Device Ech TS2G~8GCF266 Word 0 General Configuration Word 3 Default Number of Heads Word 1 Default Number of CylindersWord 6 Default Number of Sectors per Track Word 49 Capabilities Bit 13 Standby TimerTotal Sectors Addressable in LBA Mode Multiple Sector SettingTranslation Parameters Valid Current Number of Cylinders, Heads, Sectors/TrackWord 65 Minimum Multiword DMA transfer cycle time Words 82-84 Features/command sets supportedRecommended Multiword DMA transfer cycle time Word 68 Minimum PIO transfer cycle time with IordyWords 85-87 Features/command sets enabled Word 89 Time required for Security erase unit completion Word 88 Ultra DMA Modes Supported and SelectedWord 160 Power Requirement Description Word 91 Advanced power management level valueWord 128 Security Status Bit 8 Security Level Additional Requirements for CF Advanced Timing ModesTS2G~8GCF266 Idle 97h or E3h NOP 00h Idle Immediate 95h or E1hInitialize Drive Parameters 91h Read DMA C8h Read Long Sector 22h or 23h Read Buffer E4hTS2G~8GCF266 Recalibrate 1Xh Request Sense 03h Seek 7Xh Set Features EFh Feature Supported TS2G~8GCF266 Translate Sector Information Standby Immediate 94h or E0h Translate Sector 87hWear Level F5h Write Buffer E8h Write DMA CAh TS2G~8GCF266 TS2G~8GCF266 Error Posting S. Table Capacity Smart Command SetSmart Command Set Smart Feature Register Values Decription Smart Data Structure