Transcend Information TS1G-32GCF133 dimensions TS1G~32GCF133

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TS1G~32GCF133		133X CompactFlash Card

Notes: 1) All timing measurement switching points (low to high and high to low) shall be taken at 1.5 V.

2)All signal transitions for a timing parameter shall be measured at the connector specified in the measurement location column. For example, in the case of tRFS, both STROBE and –DMARDY transitions are measured at the sender connector.

3)The parameter tCYC shall be measured at the recipient’s connector farthest from the sender. 4)The parameter tLI shall be measured at the connector of the sender or recipient that is responding to an incoming transition from the recipient or sender respectively. Both the incoming signal and the outgoing response shall be measured at the same connector.

5)The parameter tAZ shall be measured at the connector of the sender or recipient that is driving the bus but must release the bus the allow for a bus turnaround.

Transcend Information Inc.

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Contents Description Placement FeaturesDimensions Transcend Block Diagram Pin Assignments and Pin Type TS1G~32GCF133 Dir Signal Description133X CompactFlash Card Signal Name Dir Pin Description Inpack Iowr VCC Wait TS1G~32GCF133 Electrical SpecificationOutput Drive Type Output Drive Characteristics Signal Interface Pull-up pin 45 BVD2 to avoid sensing their batteries as Low TS1G~32GCF133133X CompactFlash CardTable Typical Series Termination for Ultra DMA Ultra DMA Electrical RequirementsSeries termination required for Ultra DMA operation Ultra DMA Mode Cabling Requirement Attribute Memory Read Timing Specification TS1G~32GCF133 Common Memory Read Timing Specification Common Memory Write Timing Specification Input Read Timing Specification TS1G~32GCF133 Output Write Timing Specification TS1G~32GCF133 True IDE PIO Mode Read/Write Timing Specification TS1G~32GCF133 Table Ultra DMA Data Burst Timing True IDE Ultra DMA Mode Read/Write Timing SpecificationTS1G~32GCF133 TS1G~32GCF133 TS1G~32GCF133 TS1G~32GCF133 Multiple Function CompactFlash Storage Cards Card ConfigurationAttribute Memory Function Attribute Memory FunctionConfiguration Option Register Base + 00h in Attribute Memory TS1G~32GCF133 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory Transfer Function Table Pcmcia Mode I/O FunctionTable Common Memory Function Common Memory Transfer FunctionTrue IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Table Primary and Secondary I/O Decoding Primary and Secondary Address ConfigurationsTable Contiguous I/O Decoding Contiguous I/O Mapped AddressingMemory Mapped Addressing True IDE Mode AddressingData Register Address 1F0h170hOffset 0,8,9 CF-ATA RegistersSector Count Register Address 1F2h172h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Number LBA 7-0 Register Address 1F3h173h Offset Cylinder Low LBA 15-8 Register Address 1F4h174h OffsetTS1G~32GCF133 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh LBA CF-ATA Command SetDefinitions Check Power Mode 98h or E5h Erase Sectors C0h Execute Drive Diagnostic 90hFormat Track 50h Flush Cache E7hIdentify Device Ech Word Default Total Data Field Type InformationTotal Data Field Type Information Word 1 Default Number of Cylinders Word 0 General ConfigurationWord 3 Default Number of Heads Word 6 Default Number of Sectors per TrackPIO Data Transfer Cycle Timing Mode Word 49 Capabilities Bit 13 Standby TimerWords 7-8 Number of Sectors per Card Words 10-19 Serial NumberTotal Sectors Addressable in LBA Mode Multiple Sector SettingMultiword DMA transfer Word 64 Advanced PIO transfer modes supportedWord 68 Minimum PIO transfer cycle time with Iordy Words 82-84 Features/command sets supportedWord 88 Ultra DMA Modes Supported and Selected Words 85-87 Features/command sets enabledWord 160 Power Requirement Description Word 91 Advanced power management level valueWord 89 Time required for Security erase unit completion Word 128 Security Status Bit 8 Security LevelValue Value Maximum PIO mode timing selectedAdditional Requirements for CF Advanced Timing Modes Idle 97h or E3h Value Maximum Pcmcia IO timing mode SupportedValue Maximum Memory timing mode Supported NOP 00h Idle Immediate 95h or E1hInitialize Drive Parameters 91h Read DMA C8h Read Long Sector 22h or 23h Read Buffer E4hTS1G~32GCF133 Seek 7Xh Set Features EFh Feature Supported TS1G~32GCF133 Translate Sector Information Standby Immediate 94h or E0h Translate Sector 87hWear Level F5h Write Buffer E8h Write DMA CAh TS1G~32GCF133 TS1G~32GCF133 Error Posting Smart Command Set Smart Feature Register Values Smart Command SetDecription Smart Data Structure