Transcend Information TS1G-32GCF133 dimensions Wait

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TS1G~32GCF133				133X CompactFlash Card


	Signal Name	Dir.	Pin	Description
-VS1		O	33	Voltage Sense Signals. -VS1 is grounded on the Card and sensed by the Host
-VS2			40	so that the CompactFlash Storage Card CIS can be read at 3.3 volts and -VS2 is
(PC Card Memory Mode)				reserved by PCMCIA for a secondary voltage and is not connected on the Card.
-VS1				This signal is the same for all modes.
-VS2
(PC Card I/O Mode)
-VS1				This signal is the same for all modes.
-VS2
(True IDE Mode)
-WAIT		O	42	The -WAIT signal is driven low by the CompactFlash Storage Card to signal the
(PC Card Memory Mode)				host to delay completion of a memory or I/O cycle that is in progress.

-WAIT				This signal is the same as the PC Card Memory Mode signal.
(PC Card I/O Mode)

IORDY				In True IDE Mode, except in Ultra DMA modes, this output signal may be used
(True IDE Mode – Except				as IORDY.
Ultra DMA Mode)
-DDMARDY				In True IDE Mode, when Ultra DMA mode DMA Write is active, this signal is
				asserted by the host to indicate that the device is read to receive Ultra DMA
(True IDE Mode – Ultra DMA
				data-in bursts. The device may negate -DDMARDY to pause an Ultra DMA
Write Mode)
				transfer.

DSTROBE				In True IDE Mode, when Ultra DMA mode DMA Write is active, this signal is the
(True IDE Mode – Ultra				data out strobe generated by the device. Both the rising and falling edge of
DMA Read Mode)				DSTROBE cause data to be latched by the host. The device may stop

				generating DSTROBE edges to pause an Ultra DMA data-out burst.
-WE		I	36	This is a signal driven by the host and used for strobing memory write data to the
(PC Card Memory Mode)				registers of the CompactFlash Storage Card when the card is configured in the
				memory interface mode. It is also used for writing the configuration registers.
-WE				In PC Card I/O Mode, this signal is used for writing the configuration registers.
(PC Card I/O Mode)
-WE				In True IDE Mode, this input signal is not used and should be connected to VCC
(True IDE Mode)				by the host.

Transcend Information Inc.

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Contents Description Placement FeaturesDimensions Transcend Block Diagram Pin Assignments and Pin Type TS1G~32GCF133 Dir Signal Description133X CompactFlash Card Signal Name Dir Pin Description Inpack Iowr VCC Wait TS1G~32GCF133 Electrical SpecificationOutput Drive Type Output Drive Characteristics Signal Interface Pull-up pin 45 BVD2 to avoid sensing their batteries as Low TS1G~32GCF133133X CompactFlash CardTable Typical Series Termination for Ultra DMA Ultra DMA Electrical RequirementsSeries termination required for Ultra DMA operation Ultra DMA Mode Cabling Requirement Attribute Memory Read Timing Specification TS1G~32GCF133 Common Memory Read Timing Specification Common Memory Write Timing Specification Input Read Timing Specification TS1G~32GCF133 Output Write Timing Specification TS1G~32GCF133 True IDE PIO Mode Read/Write Timing Specification TS1G~32GCF133 Table Ultra DMA Data Burst Timing True IDE Ultra DMA Mode Read/Write Timing SpecificationTS1G~32GCF133 TS1G~32GCF133 TS1G~32GCF133 TS1G~32GCF133 Multiple Function CompactFlash Storage Cards Card ConfigurationAttribute Memory Function Attribute Memory FunctionConfiguration Option Register Base + 00h in Attribute Memory TS1G~32GCF133 Pin Replacement Register Base + 04h in Attribute Memory Socket and Copy Register Base + 06h in Attribute Memory Transfer Function Table Pcmcia Mode I/O FunctionTable Common Memory Function Common Memory Transfer FunctionTrue IDE Mode I/O Transfer Function Metaformat Overview CF-ATA Drive Register Set Definition and Protocol Table Primary and Secondary I/O Decoding Primary and Secondary Address ConfigurationsTable Contiguous I/O Decoding Contiguous I/O Mapped AddressingMemory Mapped Addressing True IDE Mode AddressingData Register Address 1F0h170hOffset 0,8,9 CF-ATA RegistersCylinder Low LBA 15-8 Register Address 1F4h174h Offset Feature Register Address 1F1h171h Offset 1, 0Dh Write OnlySector Count Register Address 1F2h172h Offset Sector Number LBA 7-0 Register Address 1F3h173h OffsetTS1G~32GCF133 Device Control Register Address 3F6h376h Offset Eh Card Drive Address Register Address 3F7h377h Offset Fh LBA CF-ATA Command SetDefinitions Check Power Mode 98h or E5h Erase Sectors C0h Execute Drive Diagnostic 90hFormat Track 50h Flush Cache E7hIdentify Device Ech Word Default Total Data Field Type InformationTotal Data Field Type Information Word 6 Default Number of Sectors per Track Word 0 General ConfigurationWord 1 Default Number of Cylinders Word 3 Default Number of HeadsWords 10-19 Serial Number Word 49 Capabilities Bit 13 Standby TimerPIO Data Transfer Cycle Timing Mode Words 7-8 Number of Sectors per CardWord 64 Advanced PIO transfer modes supported Multiple Sector SettingTotal Sectors Addressable in LBA Mode Multiword DMA transferWord 68 Minimum PIO transfer cycle time with Iordy Words 82-84 Features/command sets supportedWord 88 Ultra DMA Modes Supported and Selected Words 85-87 Features/command sets enabledWord 128 Security Status Bit 8 Security Level Word 91 Advanced power management level valueWord 160 Power Requirement Description Word 89 Time required for Security erase unit completionValue Value Maximum PIO mode timing selectedAdditional Requirements for CF Advanced Timing Modes Idle 97h or E3h Value Maximum Pcmcia IO timing mode SupportedValue Maximum Memory timing mode Supported NOP 00h Idle Immediate 95h or E1hInitialize Drive Parameters 91h Read DMA C8h Read Long Sector 22h or 23h Read Buffer E4hTS1G~32GCF133 Seek 7Xh Set Features EFh Feature Supported TS1G~32GCF133 Translate Sector Information Standby Immediate 94h or E0h Translate Sector 87hWear Level F5h Write Buffer E8h Write DMA CAh TS1G~32GCF133 TS1G~32GCF133 Error Posting Smart Command Set Smart Feature Register Values Smart Command SetDecription Smart Data Structure