Xilinx PCI v3.0 manual Device Initialization, Bus Width Detection

Page 29

Device Initialization

Table 3-2:Guide File Information

R

Guide File

Components

Connections

 

 

 

2vp40ff1152_64_66.ncd

153

246

 

 

 

2vp50ff1152_64_66.ncd

153

246

 

 

 

v200fg256_32_66.ncd

90

86

 

 

 

v200efg256_32_66.ncd

90

86

 

 

 

v400fg676_32_66.ncd

90

86

 

 

 

Device Initialization

Immediately after FPGA configuration, both the PCI interface and the user application are initialized by the startup mechanism present in all Virtex and Spartan devices.

During normal operation, the assertion of RST# on the PCI bus reinitializes the PCI interface and three-states all PCI bus signals. This behavior is fully compliant with the PCI Local Bus Specification. The PCI interface is designed to correctly handle asynchronous resets.

Typically, the user application must be initialized each time the PCI interface is initialized. In this case, use the RST output of the PCI interface as the asynchronous reset signal for the user application. If part of the user application requires an initialization capability that is asynchronous to PCI bus resets, simply design the user application with a separate reset signal.

Note that these reset schemes require the use of routing resources to distribute reset signals, because the global resource is not used. The use of the global reset resource is not recommended.

Bus Width Detection

A PCI interface that provides a 64-bit datapath needs to know if it is connected to a 64-bit bus or a 32-bit bus. The SLOT64 signal is an input to the PCI64 interface for this purpose.

The PCI bus specification provides a mechanism for PCI agents to determine the width of the bus by sampling the state of the REQ64# signal at the rising edge of RST#.

In embedded systems, where the bus width is known by design, the user application can simply drive SLOT64 with the appropriate value. Note that SLOT64 must never be driven with a static value; it should always be driven from the output of a flip-flop.

In designs for open systems, the bus width is not known in advance. In this case, include a separate latch or flip-flop, external to the FPGA, to sample REQ64#. Figure 3-1shows how this can be accomplished.

RESISTOR

 

 

 

REQ64#

D

Q

SLOT64

RST#

C

 

 

Figure 3-1:Sample SLOT64 Generation

PCI v3.0.151 Getting Started Guide

www.xilinx.com

29

UG157 August 31, 2005

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Contents UG157 August 31 LogiCORE PCIVersion Revision PCI v3.0.151 Getting Started Guide UG157 August 31Changes prior to v3.0, refer to v2.2.1 template set PCI v3.0.151 Getting Started Guide Table of Contents Synthesizing a Design About This Guide Guide ContentsTypographical Additional ResourcesConventions Conventions Meaning or Use Example Online DocumentPreface About This Guide Additional Documentation Getting StartedAbout the Example Design Feedback Technical SupportPCI Interface Core DocumentSystem Requirements Installing and Licensing the CoreInstalling the Core Installing and Licensing the Core Core Generator IP Updates InstallerManual Installation Core Generator IP Update Direct Download of Standalone Core Installing the CoreEvaluation Licensing OptionsFull Direct DownloadInstalling Your License File Installing Your License FileInstalling and Licensing the Core Guide File Family Specific ConsiderationsDesign Support 2S200-FG456-6C 33 MHz Pcimlc333s V300E-BG432-6C 66 MHz Pcimlc663d 2VP20-FF1152-6C/I 66 MHz Pcimlc663s 4VSX35-FF668-10C/I 33 MHz Pcimlc333g 2S50-PQ208-5C 33 MHz Pcimlc333s 2S300E-PQ208-6C 33 MHz Pcimlc333s 3S1200E-FG400-4C/I 33 MHz Pcimlc333s 4VSX35-FF668-11C/I 66 MHz Pcimlc663r Guide File Information Components Connections Family Specific ConsiderationsBus Width Detection Device InitializationInput Delay Buffers Datapath Output Clock Enable3Delay Buffer Settings Implementation Delay Setting Input Delay BuffersRegional Clock Usage Regional Clocking Illustration Regional Clock UsageBus Clock Usage Electrical Compliance Electrical ComplianceRegion Generating Bitstreams Generating BitstreamsUG157 August 31 Cadence NC-Verilog Functional SimulationFunctional Simulation Model Technology ModelSimVerilog Model Technology ModelSim VhdlInstall Path/vhdl/example/funcsim Synplicity Synplify Synthesizing a Design6Main Project Window Synthesizing a Design8Files to Add LogiCORE Files Synplicity Synplify10Main Project Window with Source Files 11Options for Implementation Device 12Create a New Project 14Select Files to Add Library 16Project Window with Source Files Exemplar LeonardoSpectrum Exemplar LeonardoSpectrumXilinx XST ISE Foundation Implementing a DesignImplementing a Design Timing Simulation Timing Simulation Install Path/vhdl/example/postsim Timing Simulation

PCI v3.0 specifications

Xilinx PCI Express (PCIe) v3.0 technology represents a significant leap in performance and efficiency for high-speed data transfer applications. As a critical interface standard for connecting peripheral devices to a host system, PCIe v3.0 introduces numerous enhancements that ensure faster data rates, increased bandwidth, and lower latency, meeting the rigorous demands of modern computing environments.

One of the standout features of PCIe v3.0 is its increased data transfer rate, which doubles the bandwidth compared to its predecessor, PCIe v2.0. This version supports a maximum theoretical bandwidth of 8 GT/s (gigatransfers per second) per lane, leading to an aggregate bandwidth of up to 32 GB/s with four lanes operating simultaneously, which is crucial for applications in data-intensive fields such as telecommunications, data centers, and high-performance computing.

Xilinx’s PCIe v3.0 solutions incorporate advanced error-handling mechanisms and improved power management. The technology employs a robust 128/130b encoding scheme that minimizes overhead while ensuring data integrity. Additionally, PCIe v3.0 supports native high-speed signaling, which not only reduces power consumption but also enhances signal quality, leading to greater reliability in data transmission.

The flexibility of Xilinx’s PCIe v3.0 implementation makes it ideal for various applications, including artificial intelligence, machine learning, and video processing, where rapid data throughput is paramount. Moreover, Xilinx provides extensive support through its Vivado Design Suite, enabling developers to easily integrate PCIe functionality into their designs while optimizing performance for specific applications through customizable settings.

Another key characteristic is the backward compatibility with earlier PCIe versions. This ensures that existing hardware can leverage new capabilities without necessitating a complete overhaul of the infrastructure, enhancing investment protection for users. The inclusion of additional features such as enhanced message signaling and the ability to support up to 64 thousand in-flight transactions further boosts the efficiency of data handling in a multi-threaded environment.

In summary, Xilinx PCI Express v3.0 technology is a powerful solution that combines high bandwidth, reduced latency, and enhanced reliability, making it an essential component for advanced computing architectures. Its robust features, coupled with Xilinx’s design tools and support, provide developers with the resources needed to push the boundaries of data transfer capabilities in a growing range of applications.
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