Xilinx PCI v3.0 manual Implementing a Design

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Chapter 6: Implementing a Design

•The par command, as provided in the script, uses a guide file in exact guide mode. Note that some designs do not require the use of guide files.

To target a different device or to use a different version of the PCI interface, see Chapter 3, “Family Specific Considerations.”

If a guide file is required, ensure that the correct guide file is used by editing the script and changing the file name. If a guide file is not required, remove the following input arguments from the par command line in the script:

-gm exact -gf ../../src/guide/guidefile.ncd

If a guide file is required, the guide file must always be used. The effort levels and delay cleanup iterations may be adjusted if necessary.

•The trce command performs a static timing analysis based on the design constraints originally specified in the user constraints file.

•The netgen command generates a simulation model of the placed and routed design.

3.Implement the design by running the appropriate script.

During initial processing trials, it is useful to enter commands one at a time from the command line rather than running the script so that you can inspect the output of each step.

If the use of a guide file is required, it is important to verify that the guiding process was successful. This may be done by inspecting the pcim_top_routed.grf file. The remainder of this section is specific to designs requiring the use of guide files.

The number of pre-routed connections should exactly match the number listed in the selection table, shown in Table 3-1, page 19. The number of unrouted signals varies depending on the size of the user application. If the number does not match, the guide process has failed. This can occur for several reasons. First, check that the correct user constraints and guide files have been used. Second, verify that the user application observes all signal-driving rules defined in the PCI User Guide.

Note: Do not attempt re-entrant routing on a guided design. Re-entrant routing must not be used as it may re-route nets that were initially guided by the guide file.

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PCI v3.0.151 Getting Started Guide

 

 

UG157 August 31, 2005

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Contents LogiCORE PCI UG157 August 31PCI v3.0.151 Getting Started Guide UG157 August 31 Version RevisionChanges prior to v3.0, refer to v2.2.1 template set PCI v3.0.151 Getting Started Guide Table of Contents Synthesizing a Design Guide Contents About This GuideAdditional Resources ConventionsTypographical Online Document Conventions Meaning or Use ExamplePreface About This Guide Getting Started About the Example DesignAdditional Documentation PCI Interface Core Technical SupportFeedback DocumentInstalling and Licensing the Core Installing the CoreSystem Requirements Core Generator IP Updates Installer Manual Installation Core Generator IP UpdateInstalling and Licensing the Core Installing the Core Direct Download of Standalone CoreFull Licensing OptionsEvaluation Direct DownloadInstalling Your License File Installing Your License FileInstalling and Licensing the Core Family Specific Considerations Design SupportGuide File 2S200-FG456-6C 33 MHz Pcimlc333s V300E-BG432-6C 66 MHz Pcimlc663d 2VP20-FF1152-6C/I 66 MHz Pcimlc663s 4VSX35-FF668-10C/I 33 MHz Pcimlc333g 2S50-PQ208-5C 33 MHz Pcimlc333s 2S300E-PQ208-6C 33 MHz Pcimlc333s 3S1200E-FG400-4C/I 33 MHz Pcimlc333s 4VSX35-FF668-11C/I 66 MHz Pcimlc663r Family Specific Considerations Guide File Information Components ConnectionsDevice Initialization Bus Width DetectionDatapath Output Clock Enable Input Delay BuffersInput Delay Buffers 3Delay Buffer Settings Implementation Delay SettingRegional Clock Usage Regional Clock Usage Regional Clocking IllustrationBus Clock Usage Electrical Compliance Electrical ComplianceRegion Generating Bitstreams Generating BitstreamsUG157 August 31 Functional Simulation Cadence NC-VerilogModel Technology ModelSim VerilogFunctional Simulation Vhdl Model Technology ModelSimInstall Path/vhdl/example/funcsim Synthesizing a Design Synplicity SynplifySynthesizing a Design 6Main Project WindowSynplicity Synplify 8Files to Add LogiCORE Files10Main Project Window with Source Files 11Options for Implementation Device 12Create a New Project 14Select Files to Add Library 16Project Window with Source Files Exemplar LeonardoSpectrum Exemplar LeonardoSpectrumXilinx XST Implementing a Design ISE FoundationImplementing a Design Timing Simulation Timing Simulation Install Path/vhdl/example/postsim Timing Simulation

PCI v3.0 specifications

Xilinx PCI Express (PCIe) v3.0 technology represents a significant leap in performance and efficiency for high-speed data transfer applications. As a critical interface standard for connecting peripheral devices to a host system, PCIe v3.0 introduces numerous enhancements that ensure faster data rates, increased bandwidth, and lower latency, meeting the rigorous demands of modern computing environments.

One of the standout features of PCIe v3.0 is its increased data transfer rate, which doubles the bandwidth compared to its predecessor, PCIe v2.0. This version supports a maximum theoretical bandwidth of 8 GT/s (gigatransfers per second) per lane, leading to an aggregate bandwidth of up to 32 GB/s with four lanes operating simultaneously, which is crucial for applications in data-intensive fields such as telecommunications, data centers, and high-performance computing.

Xilinx’s PCIe v3.0 solutions incorporate advanced error-handling mechanisms and improved power management. The technology employs a robust 128/130b encoding scheme that minimizes overhead while ensuring data integrity. Additionally, PCIe v3.0 supports native high-speed signaling, which not only reduces power consumption but also enhances signal quality, leading to greater reliability in data transmission.

The flexibility of Xilinx’s PCIe v3.0 implementation makes it ideal for various applications, including artificial intelligence, machine learning, and video processing, where rapid data throughput is paramount. Moreover, Xilinx provides extensive support through its Vivado Design Suite, enabling developers to easily integrate PCIe functionality into their designs while optimizing performance for specific applications through customizable settings.

Another key characteristic is the backward compatibility with earlier PCIe versions. This ensures that existing hardware can leverage new capabilities without necessitating a complete overhaul of the infrastructure, enhancing investment protection for users. The inclusion of additional features such as enhanced message signaling and the ability to support up to 64 thousand in-flight transactions further boosts the efficiency of data handling in a multi-threaded environment.

In summary, Xilinx PCI Express v3.0 technology is a powerful solution that combines high bandwidth, reduced latency, and enhanced reliability, making it an essential component for advanced computing architectures. Its robust features, coupled with Xilinx’s design tools and support, provide developers with the resources needed to push the boundaries of data transfer capabilities in a growing range of applications.
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