Xilinx PCI v3.0 manual Implementing a Design, ISE Foundation

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Chapter 6

Implementing a Design

This chapter describes how to implement the ping64 example design with global clocks using the supported FPGA implementation tools (included with the ISE Foundation v7.1 Development System). For the PCI 32 interface, substitute ping32 for ping64. If you are using a design with reference clocks, substitute pcim_top with pcim_top_r and ping_tb with ping_tb_r.

ISE Foundation

Before implementing a design, ensure that the Xilinx environment is properly configured and the design has been successfully synthesized.

1.Navigate to the implementation directory: cd <Install Path>/hdl/example/xilinx

This directory contains the run_xilinx script that calls the appropriate tools to place and route the example design. Scripts are provided for Unix and Microsoft Windows operating systems.

2.Review the appropriate run_xilinx script file, noting the following:

•Several required special environment variables are set at the beginning of the script; do not remove them.

•The ngdbuild command lists both ../../src/xpci search directories. The xpci directory contains a netlist the synthesis directory must contain the EDIF netlist synthesis.

and ../synthesis as of the PCI interface, and generated during design

The ngdbuild command also reads a user constraints file that corresponds to a desired target device and a particular version of the PCI interface.

•To target a different device or to use a different version of the PCI interface, the constraints file must be changed to match the device and interface selection. The available selections are defined in Chapter 3, “Family Specific Considerations.”

The user constraints files provided with the PCI interface include constraints that guarantee pinout and timing specifications. These constraints must always be used during processing.

Additional constraints that relate to the user application must be placed in this file. Before making additions to the user constraints file, back up the original so that it can be restored if necessary.

•The map command requires no special arguments, but uses an input/output register packing option.

PCI v3.0.151 Getting Started Guide

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UG157 August 31, 2005

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Contents UG157 August 31 LogiCORE PCIVersion Revision PCI v3.0.151 Getting Started Guide UG157 August 31Changes prior to v3.0, refer to v2.2.1 template set PCI v3.0.151 Getting Started Guide Table of Contents Synthesizing a Design About This Guide Guide ContentsTypographical Additional ResourcesConventions Conventions Meaning or Use Example Online DocumentPreface About This Guide Additional Documentation Getting StartedAbout the Example Design Feedback Technical SupportPCI Interface Core DocumentSystem Requirements Installing and Licensing the CoreInstalling the Core Installing and Licensing the Core Core Generator IP Updates InstallerManual Installation Core Generator IP Update Direct Download of Standalone Core Installing the CoreEvaluation Licensing OptionsFull Direct DownloadInstalling Your License File Installing Your License FileInstalling and Licensing the Core Guide File Family Specific ConsiderationsDesign Support 2S200-FG456-6C 33 MHz Pcimlc333s V300E-BG432-6C 66 MHz Pcimlc663d 2VP20-FF1152-6C/I 66 MHz Pcimlc663s 4VSX35-FF668-10C/I 33 MHz Pcimlc333g 2S50-PQ208-5C 33 MHz Pcimlc333s 2S300E-PQ208-6C 33 MHz Pcimlc333s 3S1200E-FG400-4C/I 33 MHz Pcimlc333s 4VSX35-FF668-11C/I 66 MHz Pcimlc663r Guide File Information Components Connections Family Specific ConsiderationsBus Width Detection Device InitializationInput Delay Buffers Datapath Output Clock Enable3Delay Buffer Settings Implementation Delay Setting Input Delay BuffersRegional Clock Usage Regional Clocking Illustration Regional Clock UsageBus Clock Usage Electrical Compliance Electrical ComplianceRegion Generating Bitstreams Generating BitstreamsUG157 August 31 Cadence NC-Verilog Functional SimulationFunctional Simulation Model Technology ModelSimVerilog Model Technology ModelSim VhdlInstall Path/vhdl/example/funcsim Synplicity Synplify Synthesizing a Design6Main Project Window Synthesizing a Design8Files to Add LogiCORE Files Synplicity Synplify10Main Project Window with Source Files 11Options for Implementation Device 12Create a New Project 14Select Files to Add Library 16Project Window with Source Files Exemplar LeonardoSpectrum Exemplar LeonardoSpectrumXilinx XST ISE Foundation Implementing a DesignImplementing a Design Timing Simulation Timing Simulation Install Path/vhdl/example/postsim Timing Simulation

PCI v3.0 specifications

Xilinx PCI Express (PCIe) v3.0 technology represents a significant leap in performance and efficiency for high-speed data transfer applications. As a critical interface standard for connecting peripheral devices to a host system, PCIe v3.0 introduces numerous enhancements that ensure faster data rates, increased bandwidth, and lower latency, meeting the rigorous demands of modern computing environments.

One of the standout features of PCIe v3.0 is its increased data transfer rate, which doubles the bandwidth compared to its predecessor, PCIe v2.0. This version supports a maximum theoretical bandwidth of 8 GT/s (gigatransfers per second) per lane, leading to an aggregate bandwidth of up to 32 GB/s with four lanes operating simultaneously, which is crucial for applications in data-intensive fields such as telecommunications, data centers, and high-performance computing.

Xilinx’s PCIe v3.0 solutions incorporate advanced error-handling mechanisms and improved power management. The technology employs a robust 128/130b encoding scheme that minimizes overhead while ensuring data integrity. Additionally, PCIe v3.0 supports native high-speed signaling, which not only reduces power consumption but also enhances signal quality, leading to greater reliability in data transmission.

The flexibility of Xilinx’s PCIe v3.0 implementation makes it ideal for various applications, including artificial intelligence, machine learning, and video processing, where rapid data throughput is paramount. Moreover, Xilinx provides extensive support through its Vivado Design Suite, enabling developers to easily integrate PCIe functionality into their designs while optimizing performance for specific applications through customizable settings.

Another key characteristic is the backward compatibility with earlier PCIe versions. This ensures that existing hardware can leverage new capabilities without necessitating a complete overhaul of the infrastructure, enhancing investment protection for users. The inclusion of additional features such as enhanced message signaling and the ability to support up to 64 thousand in-flight transactions further boosts the efficiency of data handling in a multi-threaded environment.

In summary, Xilinx PCI Express v3.0 technology is a powerful solution that combines high bandwidth, reduced latency, and enhanced reliability, making it an essential component for advanced computing architectures. Its robust features, coupled with Xilinx’s design tools and support, provide developers with the resources needed to push the boundaries of data transfer capabilities in a growing range of applications.
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