Texas Instruments TVP5147M1PFP Analog Input Clamping, Automatic Gain Control, Analog Video Output

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Functional Description

•Up to 10 selectable individual composite video inputs

•Up to four selectable S-video inputs

•Up to three selectable analog YPbPr video inputs and one CVBS input

•Up to two selectable analog YPbPr video inputs, two S-video inputs, and two CVBS inputs

The input selection is performed by the input select register at I2C subaddress 00h (see Section 2.11.1).

2.1.2 Analog Input Clamping

An internal clamping circuit restores the ac-coupled video signal to a fixed dc level. The clamping circuit provides line-by-line restoration of the video sync level to a fixed dc reference voltage. The selection between bottom and mid clamp is performed automatically by the TVP5147M1 decoder.

2.1.3 Automatic Gain Control

The TVP5147M1 decoder uses two programmable gain amplifiers (PGAs), one per channel. The PGA can scale a signal with a voltage-input compliance of 0.5-VPPto 2.0-VPPto a full-scale 10-bit A/D output code range. A 4-bit code sets the coarse gain with individual adjustment per channel. Minimum gain corresponds to a code 0x0 (2.0-VPPfull-scale input, −6-dB gain) while maximum gain corresponds to code 0xF (0.5 V PP full scale, +6-dB gain). The TVP5147M1 decoder also has 12-bit fine gain controls for each channel and applies independently to coarse gain controls. For composite video, the input video signal amplitude can vary significantly from the nominal level of 1 VPP. The TVP5147M1 decoder can adjust its PGA setting automatically: an automatic gain control (AGC) can be enabled and can adjust the signal amplitude such that the maximum range of the ADC is reached without clipping. Some nonstandard video signals contain peak white levels that saturate the ADC. In these cases, the AGC automatically cuts back gain to avoid clipping. If the AGC is on, then the TVP5147M1 decoder can read the gain currently being used.

The TVP5147M1 AGC comprises the front-end AGC before Y/C separation and the back-end AGC after Y/C separation. The back-end AGC restores the optimum system gain whenever an amplitude reference such as the composite peak (which is only relevant before Y/C separation) forces the front-end AGC to set the gain too low. The front-end and back-end AGC algorithms can use up to four amplitude references: sync height, color burst amplitude, composite peak, and luma peak.

The specific amplitude references being used by the front-end and back-end AGC algorithms can be independently controlled using the AGC white peak processing register located at subaddress 74h. The TVP5147M1 gain increment speed and gain increment delay can be controlled using the AGC increment speed register located at subaddress 78h and the AGC increment delay register located at subaddress 79h.

2.1.4 Analog Video Output

One of the analog input signals is available at the analog video output terminal, which is shared with input selected by I2C registers. The signal at this terminal must be buffered by a source follower. The nominal output voltage is 2 V p-p, thus the signal can be used to drive a 75-Ωline. The magnitude is maintained with an AGC in 16 steps controlled by the TVP5147M1 decoder. In order to use this function, terminal VI_1_A must be set as an output terminal. The input mode selection register also selects an active analog output signal.

2.1.5 A/D Converters

All ADCs have a resolution of 10 bits and can operate up to 30 MSPS. All A/D channels receive an identical clock from the on-chip phase-locked loop (PLL) at a frequency between 24 MHz and 30 MHz. All ADC reference voltages are generated internally.

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TVP5147M1PFP

SLES140A—March 2007

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Contents Data Manual Important Notice Contents Section 11.11 Section 11.59 Example List of Illustrations List of Tables Introduction Detailed Functionality Ordering Information TVP5147M1 ApplicationsRelated Products Packaged DevicesFunctional Block Diagram Terminal Assignments PFP Package TOP View−1. Terminal Functions Miscellaneous SignalsTerminal Functions Terminal Description Name NumberSync Signals VS/VBLK/GPIOIntroduction PGA Video Input Switch ControlAnalog Processing and A/D Converters ADCAnalog Video Output Analog Input ClampingAutomatic Gain Control 5 A/D ConvertersDigital Video Processing 1 2⋅ Decimation FilterComposite Processor NTSC/PAL CVBS/C−50 −60 −70 −10 − dB −20−30 −40 −10Luminance Processing Color Transient ImprovementOUT Clock Circuits Real-Time Control RTCOutput Formatter Terminal Separate Syncs−1. Output Format Name NumberLine 525 First Field Video VS Start FID VblkVblk Start 622 623 624 625 First Field Video VS Start Vblk Start 23 24 Vblk Stop 336 337Avid Stop Dataclk = 2⋅ Pixel Clock Mode Horizontal Blanking Cb0 Cr0 HS Start HS StopAvid Start −15. Horizontal Synchronization Signals for 20-Bit 422 Mode Avid Stop Dataclk = 1⋅ Pixel Clock Mode−3. EAV and SAV Sequence Embedded SyncsI2C Host Interface D9 MSB2 I2C Operation Reset and I2C Bus Address SelectionVbus Access −4. I 2C Host Interface Terminal DescriptionVbus HostI2C WSS VitcVBI Data Processor −6. Supported VBI SystemVBI System Standard Line Number Number of Bytes Byte Description VBI Fifo and Ancillary Data in Video Stream−7. Ancillary Data Format and Sequence LSBVBI Raw Data Output Reset and Initialization−9. Reset Sequence −8. VBI Raw Data Output FormatInternal Control Registers Adjusting External SyncsRegister Name 2C Subaddress Default −10. I 2C Register SummaryVblk start line V bit control 75h 12h VCR trick mode control 76h −11. Vbus Register Summary Register Definitions −12. Analog Channel and Video Mode SelectionMode Inputs Selected Input Select Output HEX Input Select RegisterAFE Gain Control Register Video Standard RegisterCvbs and S-Video Component Video Operation Mode Register Autoswitch Mask RegisterSubaddress 03h Default 00h Color Killer Register Luminance Processing Control 1 RegisterLuminance Processing Control 3 Register Subaddress 08h Default 02h Reserved Trap filter selectLuminance Processing Control 2 Register Luminance Brightness RegisterChroma Hue Register Luminance Contrast RegisterChrominance Saturation Register Chrominance Processing Control 1 RegisterAvid Start Pixel Register Subaddress 0Eh DefaultChrominance Processing Control 2 Register WCFHsync Stop Pixel Register Avid Stop Pixel RegisterHsync Start Pixel Register Vsync Start Line RegisterVblk Start Line Register CTI Delay RegisterVsync Stop Line Register Vblk Stop Line RegisterSubaddress 2Eh Default 00h CTI coring CTI gain CTI Control RegisterSync Control Register Output Formatter 2 Register Subaddress 33h Default 40hOutput Formatter 1 Register CbCr code ReservedOutput Formatter 3 Register Output Formatter 4 Register Output Formatter 5 Register Subaddress 39h Default 00h Output Formatter 6 RegisterClear Lost Lock Detect Register Status 1 Register Read onlyColor killed Status 2 RegisterAGC Gain Status Register Subaddress 3Ch Fine gain 3Dh Coarse gainVideo Standard Status Register Gpio Input 1 RegisterGpio Input 2 Register Glco FIDAFE Coarse Gain for CH 1 Register Subaddress 46h Default 20h Cgain 1 ReservedSubaddress 47h Default 20h Cgain 2 Reserved AFE Coarse Gain for CH 2 RegisterAFE Coarse Gain for CH 3 Register Subaddress 48h Default 20h Cgain 3 ReservedSubaddress 49h Default 20h Cgain 4 Reserved AFE Coarse Gain for CH 4 RegisterAFE Fine Gain for Pb Register AFE Fine Gain for YChroma RegisterAFE Fine Gain for Pr Register Field ID Control Register Subaddress 57h Default 00hAFE Fine Gain for CVBSLuma Register FID controlReg 69h Reg 75h Mode Standard LPF Nonstandard LPF Bit Subaddress 69h Default 00hBit mode Bit and V-bit Control 1 RegisterBack-End AGC Control Register AGC Decrement Speed Control RegisterROM Version Register Subaddress 74h Default 00h Luma peak a AGC White Peak Processing RegisterLuma peak B Composite peak V Bit Control Register Lines per frame BitHorizontal Shake Increment Register VCR Trick Mode Control RegisterAGC Increment Delay Register AGC Increment Speed RegisterChip ID LSB Register Analog Output Control 1 RegisterChip ID MSB Register Cpll Speed Control RegisterAGC Decrement Delay Register Status Request RegisterVertical Line Count Register VDP TTX Filter And Mask Registers VDP TTX Filter Control Register Filter VDP Fifo Word Count RegisterNibble PassVDP Fifo Output Control Register VDP Fifo Reset RegisterVDP Fifo Interrupt Threshold Register VDP Line Number Interrupt RegisterVDP Line Start Register VDP Global Line Mode RegisterVDP Pixel Alignment Register VDP Line Stop RegisterVbus Data Access With No Vbus Address Increment Register VDP Full Field Enable RegisterVDP Full Field Mode Register Vbus Data Access With Vbus Address Increment RegisterInterrupt Raw Status 0 Register Vbus Address Access RegisterFifo Read Data Register Fifo Thrs TTX WSS VPS Vitc CC F2 CC F1Reserved Lock Interrupt Raw Status 1 RegisterInterrupt Status 0 Register Fifo fullInterrupt Status 1 Register Interrupt Mask 0 Register Subaddress F5h Default 00h Interrupt Mask 1 RegisterInterrupt Clear 0 Register Subaddress F7h Default 00h Interrupt Clear 1 RegisterVDP WSS Data Register Vbus Register DefinitionsVDP Closed Caption Data Register Subaddress ByteVDP Vitc Data Register VDP V-Chip TV Rating Block 1 RegisterVDP V-Chip TV Rating Block 2 Register None VDP V-Chip TV Rating Block 3 RegisterVDP V-CHIP Mpaa Rating Data Register TV-PGVDP General Line Mode and Line Address Register Default line mode = FFh, address = 00hVDP VPS/Gemstar Data Register VPS Read onlyInterrupt Configuration Register Analog Output Control 2 RegisterAbsolute Maximum Ratings† Crystal SpecificationsCrystal Specifications MIN NOM MAX Unit Recommended Operating ConditionsAnalog Processing and A/D Converters Electrical CharacteristicsDC Electrical Characteristics see Note Parameter Test Conditions MIN TYP MAX UnitVOH VOL TimingDataclk AVID, VS, HS, FID VC1 SDA VC0 SCLElectrical Specifications Recommended Settings ExampleAssumptions Assumptions Example Register Settings Example Register Settings Application Example −1. Example Application CircuitDesigning With PowerPADt Devices Orderable Device Status Package Pins Package Eco Plan MSL Peak TempQty Page

TVP5147M1PFP specifications

The Texas Instruments TVP5147M1PFP is a versatile video decoder that stands out in the realm of analog video processing. This device is particularly designed for high-quality video applications, making it an excellent choice for a variety of consumer and professional electronics that require reliable video decoding capabilities.

One of the main features of the TVP5147 is its ability to decode multiple video formats, including NTSC, PAL, and SECAM. This flexibility allows the decoder to seamlessly interface with various video sources from different geographic regions, providing a global solution for video applications. The TVP5147 includes advanced synchronization features, ensuring it can effectively handle video signals that may vary in timing and quality.

The device is equipped with a sophisticated 10-bit analog-to-digital converter (ADC), which enhances the precision and clarity of the digital video output. This high-resolution capability allows for improved color accuracy and detail, leading to a more lifelike video representation. Additionally, the TVP5147 utilizes advanced digital processing technologies, including noise reduction and image enhancement features, contributing to outstanding image quality even in less than ideal input conditions.

Another notable characteristic of the TVP5147M1PFP is its support for various output formats, including ITU-R BT.601 and 656, which facilitates easy integration into different systems. The device can also provide various output resolutions, catering to the needs of diverse applications ranging from standard definition to high definition displays.

In terms of connectivity, the TVP5147 offers multiple input options, including composite video, S-video, and component video interfaces. This versatility ensures that it can accommodate a wide range of video sources, from traditional VHS players to modern digital cameras. Furthermore, the integrated video control features allow for easy adjustment of parameters such as brightness, contrast, and saturation.

The power consumption of the TVP5147M1PFP is optimized for low-energy applications while maintaining high performance, making it suitable for battery-powered devices and energy-efficient designs. Overall, the Texas Instruments TVP5147M1PFP is an exceptional video decoder that blends flexibility, high quality, and advanced technology, making it a preferred choice for video processing in numerous consumer and industrial applications. Its combination of features ensures reliable performance and high-quality output, fulfilling the demands of modern multimedia environments.
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