Texas Instruments TVP5147M1PFP manual Clock Circuits, Real-Time Control RTC, Output Formatter

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Functional Description

2.3Clock Circuits

An internal line-locked PLL generates the system and pixel clocks. A 14.318-MHz clock is required to drive the PLL. This can be input to the TVP5147M1 decoder at the 1.8-V level on terminal 74 (XTAL1), or a crystal of 14.318-MHz fundamental resonant frequency can be connected across terminals 74 and 75 (XTAL2). If a parallel resonant circuit is used as shown in Figure 2−10, then the external capacitors must have the following relationship:

CL1 = CL2 = 2CL − C STRAY,

where CSTRAY is the terminal capacitance with respect to ground. Figure 2−10 shows the reference clock configurations. The TVP5147M1 decoder generates the DATACLK signal used for clocking data.

TVP5147M1

XTAL1

7414.318-MHz Clock

TVP5147M1

XTAL1

74

14.318-MHz

Crystal CL1

XTAL2

75

XTAL2

75

CL2

Figure 2−10. Reference Clock Configurations

2.4Real-Time Control (RTC)

Although the TVP5147M1 decoder is a line-locked system, the color burst information is used to determine accurately the color subcarrier frequency and phase. This ensures proper operation with nonstandard video signals that do not follow exactly the required frequency multiple between color subcarrier frequency and video line frequency. The frequency control word of the internal color subcarrier PLL and the subcarrier reset bit are transmitted via terminal 37 (GLCO) for optional use in an end system (for example, by a video encoder). The frequency control word is a 23-bit binary number. The instantaneous frequency of the color subcarrier can be calculated using the following equation:

F

PLL

+

Fctrl

F

sclk

 

 

223

 

where FPLL is the frequency of the subcarrier PLL, Fctrl is the 23-bit PLL frequency control word, and Fsclk is two times the pixel frequency. This information can be generated on the GLCO terminal. Figure 2−11 shows

the detailed timing diagram.

Valid

Invalid

Sample

Sample

Reserved

RTC

128 CLK

18 CLK

1 CLK

Start

Bit

M

L

S R

S

S

B

B

 

22

0

 

45 CLK 3 CLK 23-Bit Fsc PLL Increment

NOTE:

RTC reset bit (R) is active-low, Sequence bit (S) PAL: 1 = (R-Y) line normal, 0 = (R-Y) line inverted, NTSC: 1 = no change

Figure 2−11. RTC Timing

2.5Output Formatter

The output formatter sets how the data is formatted for output on the TVP5147M1 output buses. Table 2−1 shows the available output modes.

SLES140A—March 2007

TVP5147M1PFP

15

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Contents Data Manual Important Notice Contents Section 11.11 Section 11.59 Example List of Illustrations List of Tables Introduction Detailed Functionality Packaged Devices TVP5147M1 ApplicationsRelated Products Ordering InformationFunctional Block Diagram PFP Package TOP View Terminal AssignmentsTerminal Description Name Number Miscellaneous SignalsTerminal Functions −1. Terminal FunctionsVS/VBLK/GPIO Sync SignalsIntroduction ADC Video Input Switch ControlAnalog Processing and A/D Converters PGA5 A/D Converters Analog Input ClampingAutomatic Gain Control Analog Video OutputComposite Processor Digital Video Processing1 2⋅ Decimation Filter CVBS/C NTSC/PAL−10 −10 − dB −20−30 −40 −50 −60 −70OUT Luminance ProcessingColor Transient Improvement Output Formatter Clock CircuitsReal-Time Control RTC Name Number Separate Syncs−1. Output Format TerminalVblk Start Line 525 First Field Video VS StartFID Vblk Vblk Start 23 24 Vblk Stop 336 337 622 623 624 625 First Field Video VS StartAvid Start Avid Stop Dataclk = 2⋅ Pixel Clock ModeHorizontal Blanking Cb0 Cr0 HS Start HS Stop Avid Stop Dataclk = 1⋅ Pixel Clock Mode −15. Horizontal Synchronization Signals for 20-Bit 422 ModeD9 MSB Embedded SyncsI2C Host Interface −3. EAV and SAV Sequence−4. I 2C Host Interface Terminal Description Reset and I2C Bus Address SelectionVbus Access 2 I2C OperationWSS Vitc HostI2C VbusVBI System Standard Line Number Number of Bytes VBI Data Processor−6. Supported VBI System LSB VBI Fifo and Ancillary Data in Video Stream−7. Ancillary Data Format and Sequence Byte Description−8. VBI Raw Data Output Format Reset and Initialization−9. Reset Sequence VBI Raw Data Output−10. I 2C Register Summary Adjusting External SyncsRegister Name 2C Subaddress Default Internal Control RegistersVblk start line V bit control 75h 12h VCR trick mode control 76h −11. Vbus Register Summary Input Select Register −12. Analog Channel and Video Mode SelectionMode Inputs Selected Input Select Output HEX Register DefinitionsCvbs and S-Video Component Video AFE Gain Control RegisterVideo Standard Register Subaddress 03h Default 00h Operation Mode RegisterAutoswitch Mask Register Luminance Processing Control 1 Register Color Killer RegisterLuminance Brightness Register Subaddress 08h Default 02h Reserved Trap filter selectLuminance Processing Control 2 Register Luminance Processing Control 3 RegisterChrominance Processing Control 1 Register Luminance Contrast RegisterChrominance Saturation Register Chroma Hue RegisterWCF Subaddress 0Eh DefaultChrominance Processing Control 2 Register Avid Start Pixel RegisterVsync Start Line Register Avid Stop Pixel RegisterHsync Start Pixel Register Hsync Stop Pixel RegisterVblk Stop Line Register CTI Delay RegisterVsync Stop Line Register Vblk Start Line RegisterSync Control Register Subaddress 2Eh Default 00h CTI coring CTI gainCTI Control Register CbCr code Reserved Subaddress 33h Default 40hOutput Formatter 1 Register Output Formatter 2 RegisterOutput Formatter 3 Register Output Formatter 4 Register Output Formatter 5 Register Clear Lost Lock Detect Register Subaddress 39h Default 00hOutput Formatter 6 Register Read only Status 1 RegisterSubaddress 3Ch Fine gain 3Dh Coarse gain Status 2 RegisterAGC Gain Status Register Color killedGpio Input 1 Register Video Standard Status RegisterGlco FID Gpio Input 2 RegisterAFE Coarse Gain for CH 2 Register Subaddress 46h Default 20h Cgain 1 ReservedSubaddress 47h Default 20h Cgain 2 Reserved AFE Coarse Gain for CH 1 RegisterAFE Coarse Gain for CH 4 Register Subaddress 48h Default 20h Cgain 3 ReservedSubaddress 49h Default 20h Cgain 4 Reserved AFE Coarse Gain for CH 3 RegisterAFE Fine Gain for Pr Register AFE Fine Gain for Pb RegisterAFE Fine Gain for YChroma Register FID control Subaddress 57h Default 00hAFE Fine Gain for CVBSLuma Register Field ID Control RegisterBit and V-bit Control 1 Register Subaddress 69h Default 00hBit mode Reg 69h Reg 75h Mode Standard LPF Nonstandard LPF BitROM Version Register Back-End AGC Control RegisterAGC Decrement Speed Control Register Luma peak B Composite peak Subaddress 74h Default 00h Luma peak aAGC White Peak Processing Register Lines per frame Bit V Bit Control RegisterAGC Increment Speed Register VCR Trick Mode Control RegisterAGC Increment Delay Register Horizontal Shake Increment RegisterCpll Speed Control Register Analog Output Control 1 RegisterChip ID MSB Register Chip ID LSB RegisterVertical Line Count Register AGC Decrement Delay RegisterStatus Request Register VDP TTX Filter And Mask Registers VDP TTX Filter Control Register Pass VDP Fifo Word Count RegisterNibble FilterVDP Line Number Interrupt Register VDP Fifo Reset RegisterVDP Fifo Interrupt Threshold Register VDP Fifo Output Control RegisterVDP Line Stop Register VDP Global Line Mode RegisterVDP Pixel Alignment Register VDP Line Start RegisterVbus Data Access With Vbus Address Increment Register VDP Full Field Enable RegisterVDP Full Field Mode Register Vbus Data Access With No Vbus Address Increment RegisterFifo Thrs TTX WSS VPS Vitc CC F2 CC F1 Vbus Address Access RegisterFifo Read Data Register Interrupt Raw Status 0 RegisterFifo full Interrupt Raw Status 1 RegisterInterrupt Status 0 Register Reserved LockInterrupt Status 1 Register Interrupt Mask 0 Register Interrupt Clear 0 Register Subaddress F5h Default 00hInterrupt Mask 1 Register Interrupt Clear 1 Register Subaddress F7h Default 00hSubaddress Byte Vbus Register DefinitionsVDP Closed Caption Data Register VDP WSS Data RegisterVDP V-Chip TV Rating Block 2 Register VDP Vitc Data RegisterVDP V-Chip TV Rating Block 1 Register TV-PG VDP V-Chip TV Rating Block 3 RegisterVDP V-CHIP Mpaa Rating Data Register NoneDefault line mode = FFh, address = 00h VDP General Line Mode and Line Address RegisterVPS Read only VDP VPS/Gemstar Data RegisterAnalog Output Control 2 Register Interrupt Configuration RegisterRecommended Operating Conditions Crystal SpecificationsCrystal Specifications MIN NOM MAX Unit Absolute Maximum Ratings†Parameter Test Conditions MIN TYP MAX Unit Electrical CharacteristicsDC Electrical Characteristics see Note Analog Processing and A/D ConvertersVC1 SDA VC0 SCL TimingDataclk AVID, VS, HS, FID VOH VOLElectrical Specifications Assumptions Recommended SettingsExample Assumptions Example Register Settings Example Register Settings −1. Example Application Circuit Application ExampleDesigning With PowerPADt Devices Qty Orderable Device Status Package Pins Package Eco PlanMSL Peak Temp Page

TVP5147M1PFP specifications

The Texas Instruments TVP5147M1PFP is a versatile video decoder that stands out in the realm of analog video processing. This device is particularly designed for high-quality video applications, making it an excellent choice for a variety of consumer and professional electronics that require reliable video decoding capabilities.

One of the main features of the TVP5147 is its ability to decode multiple video formats, including NTSC, PAL, and SECAM. This flexibility allows the decoder to seamlessly interface with various video sources from different geographic regions, providing a global solution for video applications. The TVP5147 includes advanced synchronization features, ensuring it can effectively handle video signals that may vary in timing and quality.

The device is equipped with a sophisticated 10-bit analog-to-digital converter (ADC), which enhances the precision and clarity of the digital video output. This high-resolution capability allows for improved color accuracy and detail, leading to a more lifelike video representation. Additionally, the TVP5147 utilizes advanced digital processing technologies, including noise reduction and image enhancement features, contributing to outstanding image quality even in less than ideal input conditions.

Another notable characteristic of the TVP5147M1PFP is its support for various output formats, including ITU-R BT.601 and 656, which facilitates easy integration into different systems. The device can also provide various output resolutions, catering to the needs of diverse applications ranging from standard definition to high definition displays.

In terms of connectivity, the TVP5147 offers multiple input options, including composite video, S-video, and component video interfaces. This versatility ensures that it can accommodate a wide range of video sources, from traditional VHS players to modern digital cameras. Furthermore, the integrated video control features allow for easy adjustment of parameters such as brightness, contrast, and saturation.

The power consumption of the TVP5147M1PFP is optimized for low-energy applications while maintaining high performance, making it suitable for battery-powered devices and energy-efficient designs. Overall, the Texas Instruments TVP5147M1PFP is an exceptional video decoder that blends flexibility, high quality, and advanced technology, making it a preferred choice for video processing in numerous consumer and industrial applications. Its combination of features ensures reliable performance and high-quality output, fulfilling the demands of modern multimedia environments.
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