Texas Instruments TVP5147M1PFP manual Embedded Syncs, I2C Host Interface, 3. EAV and SAV Sequence

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Functional Description

HS

First Field

VS

HS

Second Field

VS

B/2

H/2 + B/2

B/2

H/2 + B/2

 

10-Bit (PCLK = 2⋅ Pixel Clock)

20-Bit (PCLK = 1⋅ Pixel Clock)

 

 

 

 

 

Mode

B/2

H/2

B/2

H/2

 

 

 

 

 

NTSC 601

64

858

32

429

 

 

 

 

 

PAL 601

64

864

32

432

 

 

 

 

 

Figure 2−16. VSYNC Position With Respect to HSYNC

2.5.2 Embedded Syncs

Standards with embedded syncs insert the SAV and EAV codes into the data stream on the rising and falling edges of AVID. These codes contain the V and F bits which also define vertical timing. Table 2−3 gives the format of the SAV and EAV codes.

H equals 1 always indicates EAV. H equals 0 always indicates SAV. The alignment of V and F to the line and field counter varies depending on the standard.

The P bits are protection bits:

P3 = V xor H; P2 = F xor H; P1 = F xor V; P0 = F xor V xor H

Table 2−3. EAV and SAV Sequence

 

D9 (MSB)

D8

D7

D6

D5

D4

D3

D2

D1

D0

 

 

 

 

 

 

 

 

 

 

 

Preamble

1

1

1

1

1

1

1

1

1

1

 

 

 

 

 

 

 

 

 

 

 

Preamble

0

0

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

Preamble

0

0

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

Status word

1

F

V

H

P3

P2

P1

P0

0

0

2.6I2C Host Interface

Communication with the TVP5147M1 decoder is via an I2C host interface. The I2C standard consists of two signals, the serial input/output data (SDA) line and the serial input clock line (SCL), which carry information between the devices connected to the bus. A third signal (I2CA) is used for slave address selection. Although an I2C system can be multimastered, the TVP5147M1 decoder functions as a slave device only.

Because SDA and SCL are kept open-drain at a logic-high output level or when the bus is not driven, the user must connect SDA and SCL to a positive supply voltage via a pullup resistor on the board. The slave addresses select signal, terminal 37 (I2CA), enables the use of two TVP5147M1 devices tied to the same I2C bus, because it controls the least significant bit of the I2C device address.

SLES140A—March 2007

TVP5147M1PFP

21

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Contents Data Manual Important Notice Contents Section 11.11 Section 11.59 Example List of Illustrations List of Tables Introduction Detailed Functionality Related Products TVP5147M1 ApplicationsOrdering Information Packaged DevicesFunctional Block Diagram PFP Package TOP View Terminal AssignmentsTerminal Functions Miscellaneous Signals−1. Terminal Functions Terminal Description Name NumberVS/VBLK/GPIO Sync SignalsIntroduction Analog Processing and A/D Converters Video Input Switch ControlPGA ADCAutomatic Gain Control Analog Input ClampingAnalog Video Output 5 A/D ConvertersComposite Processor Digital Video Processing1 2⋅ Decimation Filter CVBS/C NTSC/PAL−30 −40 −10 − dB −20−50 −60 −70 −10OUT Luminance ProcessingColor Transient Improvement Output Formatter Clock CircuitsReal-Time Control RTC −1. Output Format Separate SyncsTerminal Name NumberVblk Start Line 525 First Field Video VS StartFID Vblk Vblk Start 23 24 Vblk Stop 336 337 622 623 624 625 First Field Video VS StartAvid Start Avid Stop Dataclk = 2⋅ Pixel Clock ModeHorizontal Blanking Cb0 Cr0 HS Start HS Stop Avid Stop Dataclk = 1⋅ Pixel Clock Mode −15. Horizontal Synchronization Signals for 20-Bit 422 ModeI2C Host Interface Embedded Syncs−3. EAV and SAV Sequence D9 MSBVbus Access Reset and I2C Bus Address Selection2 I2C Operation −4. I 2C Host Interface Terminal DescriptionI2C HostVbus WSS VitcVBI System Standard Line Number Number of Bytes VBI Data Processor−6. Supported VBI System −7. Ancillary Data Format and Sequence VBI Fifo and Ancillary Data in Video StreamByte Description LSB−9. Reset Sequence Reset and InitializationVBI Raw Data Output −8. VBI Raw Data Output FormatRegister Name 2C Subaddress Default Adjusting External SyncsInternal Control Registers −10. I 2C Register SummaryVblk start line V bit control 75h 12h VCR trick mode control 76h −11. Vbus Register Summary Mode Inputs Selected Input Select Output HEX −12. Analog Channel and Video Mode SelectionRegister Definitions Input Select RegisterCvbs and S-Video Component Video AFE Gain Control RegisterVideo Standard Register Subaddress 03h Default 00h Operation Mode RegisterAutoswitch Mask Register Luminance Processing Control 1 Register Color Killer RegisterLuminance Processing Control 2 Register Subaddress 08h Default 02h Reserved Trap filter selectLuminance Processing Control 3 Register Luminance Brightness RegisterChrominance Saturation Register Luminance Contrast RegisterChroma Hue Register Chrominance Processing Control 1 RegisterChrominance Processing Control 2 Register Subaddress 0Eh DefaultAvid Start Pixel Register WCFHsync Start Pixel Register Avid Stop Pixel RegisterHsync Stop Pixel Register Vsync Start Line RegisterVsync Stop Line Register CTI Delay RegisterVblk Start Line Register Vblk Stop Line RegisterSync Control Register Subaddress 2Eh Default 00h CTI coring CTI gainCTI Control Register Output Formatter 1 Register Subaddress 33h Default 40hOutput Formatter 2 Register CbCr code ReservedOutput Formatter 3 Register Output Formatter 4 Register Output Formatter 5 Register Clear Lost Lock Detect Register Subaddress 39h Default 00hOutput Formatter 6 Register Read only Status 1 RegisterAGC Gain Status Register Status 2 RegisterColor killed Subaddress 3Ch Fine gain 3Dh Coarse gainGpio Input 1 Register Video Standard Status RegisterGlco FID Gpio Input 2 RegisterSubaddress 47h Default 20h Cgain 2 Reserved Subaddress 46h Default 20h Cgain 1 ReservedAFE Coarse Gain for CH 1 Register AFE Coarse Gain for CH 2 RegisterSubaddress 49h Default 20h Cgain 4 Reserved Subaddress 48h Default 20h Cgain 3 ReservedAFE Coarse Gain for CH 3 Register AFE Coarse Gain for CH 4 RegisterAFE Fine Gain for Pr Register AFE Fine Gain for Pb RegisterAFE Fine Gain for YChroma Register AFE Fine Gain for CVBSLuma Register Subaddress 57h Default 00hField ID Control Register FID controlBit mode Subaddress 69h Default 00hReg 69h Reg 75h Mode Standard LPF Nonstandard LPF Bit Bit and V-bit Control 1 RegisterROM Version Register Back-End AGC Control RegisterAGC Decrement Speed Control Register Luma peak B Composite peak Subaddress 74h Default 00h Luma peak aAGC White Peak Processing Register Lines per frame Bit V Bit Control RegisterAGC Increment Delay Register VCR Trick Mode Control RegisterHorizontal Shake Increment Register AGC Increment Speed RegisterChip ID MSB Register Analog Output Control 1 RegisterChip ID LSB Register Cpll Speed Control RegisterVertical Line Count Register AGC Decrement Delay RegisterStatus Request Register VDP TTX Filter And Mask Registers VDP TTX Filter Control Register Nibble VDP Fifo Word Count RegisterFilter PassVDP Fifo Interrupt Threshold Register VDP Fifo Reset RegisterVDP Fifo Output Control Register VDP Line Number Interrupt RegisterVDP Pixel Alignment Register VDP Global Line Mode RegisterVDP Line Start Register VDP Line Stop RegisterVDP Full Field Mode Register VDP Full Field Enable RegisterVbus Data Access With No Vbus Address Increment Register Vbus Data Access With Vbus Address Increment RegisterFifo Read Data Register Vbus Address Access RegisterInterrupt Raw Status 0 Register Fifo Thrs TTX WSS VPS Vitc CC F2 CC F1Interrupt Status 0 Register Interrupt Raw Status 1 RegisterReserved Lock Fifo fullInterrupt Status 1 Register Interrupt Mask 0 Register Interrupt Clear 0 Register Subaddress F5h Default 00hInterrupt Mask 1 Register Interrupt Clear 1 Register Subaddress F7h Default 00hVDP Closed Caption Data Register Vbus Register DefinitionsVDP WSS Data Register Subaddress ByteVDP V-Chip TV Rating Block 2 Register VDP Vitc Data RegisterVDP V-Chip TV Rating Block 1 Register VDP V-CHIP Mpaa Rating Data Register VDP V-Chip TV Rating Block 3 RegisterNone TV-PGDefault line mode = FFh, address = 00h VDP General Line Mode and Line Address RegisterVPS Read only VDP VPS/Gemstar Data RegisterAnalog Output Control 2 Register Interrupt Configuration RegisterCrystal Specifications MIN NOM MAX Unit Crystal SpecificationsAbsolute Maximum Ratings† Recommended Operating ConditionsDC Electrical Characteristics see Note Electrical CharacteristicsAnalog Processing and A/D Converters Parameter Test Conditions MIN TYP MAX UnitDataclk AVID, VS, HS, FID TimingVOH VOL VC1 SDA VC0 SCLElectrical Specifications Assumptions Recommended SettingsExample Assumptions Example Register Settings Example Register Settings −1. Example Application Circuit Application ExampleDesigning With PowerPADt Devices Qty Orderable Device Status Package Pins Package Eco PlanMSL Peak Temp Page

TVP5147M1PFP specifications

The Texas Instruments TVP5147M1PFP is a versatile video decoder that stands out in the realm of analog video processing. This device is particularly designed for high-quality video applications, making it an excellent choice for a variety of consumer and professional electronics that require reliable video decoding capabilities.

One of the main features of the TVP5147 is its ability to decode multiple video formats, including NTSC, PAL, and SECAM. This flexibility allows the decoder to seamlessly interface with various video sources from different geographic regions, providing a global solution for video applications. The TVP5147 includes advanced synchronization features, ensuring it can effectively handle video signals that may vary in timing and quality.

The device is equipped with a sophisticated 10-bit analog-to-digital converter (ADC), which enhances the precision and clarity of the digital video output. This high-resolution capability allows for improved color accuracy and detail, leading to a more lifelike video representation. Additionally, the TVP5147 utilizes advanced digital processing technologies, including noise reduction and image enhancement features, contributing to outstanding image quality even in less than ideal input conditions.

Another notable characteristic of the TVP5147M1PFP is its support for various output formats, including ITU-R BT.601 and 656, which facilitates easy integration into different systems. The device can also provide various output resolutions, catering to the needs of diverse applications ranging from standard definition to high definition displays.

In terms of connectivity, the TVP5147 offers multiple input options, including composite video, S-video, and component video interfaces. This versatility ensures that it can accommodate a wide range of video sources, from traditional VHS players to modern digital cameras. Furthermore, the integrated video control features allow for easy adjustment of parameters such as brightness, contrast, and saturation.

The power consumption of the TVP5147M1PFP is optimized for low-energy applications while maintaining high performance, making it suitable for battery-powered devices and energy-efficient designs. Overall, the Texas Instruments TVP5147M1PFP is an exceptional video decoder that blends flexibility, high quality, and advanced technology, making it a preferred choice for video processing in numerous consumer and industrial applications. Its combination of features ensures reliable performance and high-quality output, fulfilling the demands of modern multimedia environments.
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