Texas Instruments TVP5147M1PFP Reset and I2C Bus Address Selection, 2 I2C Operation, Vbus Access

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Functional Description

Table 2−4. I 2C Host Interface Terminal Description

SIGNAL

TYPE

DESCRIPTION

 

 

 

I2CA

I

Slave address selection

 

 

 

SCL

I

Input clock line

 

 

 

SDA

I/O

Input/output data line

2.6.1 Reset and I2C Bus Address Selection

The TVP5147M1 decoder can respond to two possible chip addresses. The address selection is made at reset by an externally supplied level on the I2CA terminal. The TVP5147M1 decoder samples the level of terminal 37 at power up or at the trailing edge of RESETB and configures the I2C bus address bit A0. The I2CA terminal has an internal pulldown resistor to pull the terminal low to set a zero.

Table 2−5. I 2C Address Selection

A6

A5

A4

A3

A2

A1

A0 (I2CA)

R/W

HEX

 

 

 

 

 

 

 

 

 

1

0

1

1

1

0

0 (default)

1/0

B9/B8

 

 

 

 

 

 

 

 

 

1

0

1

1

1

0

1 †

1/0

BB/BA

†If terminal 37 is strapped to DVDD via a 2.2-kΩresistor, I2C device address A0 is set to 1.

2.6.2 I2C Operation

Data transfers occur using the following illustrated formats.

S

10111000

ACK

Subaddress

ACK

Send data

ACK

P

Read from I2C control registers

S

10111000 ACK

Subaddress

ACK

S

10111001

ACK

Receive data

NAK

P

S = I2C bus start condition P = I2C bus stop condition

ACK = Acknowledge generated by the slave

NAK = Acknowledge generated by the master, for multiple-byte read master with ACK each byte except last byte

Subaddress = Subaddress byte

Data = Data byte. If more than one byte of data is transmitted (read and write), the subaddress pointer is automatically incremented.

I2C bus address = Example shown that I2CA is in default mode. Write (B8h), read (B9h)

2.6.3 VBUS Access

The TVP5147M1 decoder has additional internal registers accessible through an indirect access to an internal 24-bit address wide VBUS. Figure 2−17 shows the VBUS register access.

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TVP5147M1PFP

SLES140A—March 2007

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Contents Data Manual Important Notice Contents Section 11.11 Section 11.59 Example List of Illustrations List of Tables Introduction Detailed Functionality Ordering Information TVP5147M1 ApplicationsRelated Products Packaged DevicesFunctional Block Diagram Terminal Assignments PFP Package TOP View−1. Terminal Functions Miscellaneous SignalsTerminal Functions Terminal Description Name NumberSync Signals VS/VBLK/GPIOIntroduction PGA Video Input Switch ControlAnalog Processing and A/D Converters ADCAnalog Video Output Analog Input ClampingAutomatic Gain Control 5 A/D ConvertersDigital Video Processing 1 2⋅ Decimation FilterComposite Processor NTSC/PAL CVBS/C−50 −60 −70 −10 − dB −20−30 −40 −10Luminance Processing Color Transient ImprovementOUT Clock Circuits Real-Time Control RTCOutput Formatter Terminal Separate Syncs−1. Output Format Name NumberLine 525 First Field Video VS Start FID VblkVblk Start 622 623 624 625 First Field Video VS Start Vblk Start 23 24 Vblk Stop 336 337Avid Stop Dataclk = 2⋅ Pixel Clock Mode Horizontal Blanking Cb0 Cr0 HS Start HS StopAvid Start −15. Horizontal Synchronization Signals for 20-Bit 422 Mode Avid Stop Dataclk = 1⋅ Pixel Clock Mode−3. EAV and SAV Sequence Embedded SyncsI2C Host Interface D9 MSB2 I2C Operation Reset and I2C Bus Address SelectionVbus Access −4. I 2C Host Interface Terminal DescriptionVbus HostI2C WSS VitcVBI Data Processor −6. Supported VBI SystemVBI System Standard Line Number Number of Bytes Byte Description VBI Fifo and Ancillary Data in Video Stream−7. Ancillary Data Format and Sequence LSBVBI Raw Data Output Reset and Initialization−9. Reset Sequence −8. VBI Raw Data Output FormatInternal Control Registers Adjusting External SyncsRegister Name 2C Subaddress Default −10. I 2C Register SummaryVblk start line V bit control 75h 12h VCR trick mode control 76h −11. Vbus Register Summary Register Definitions −12. Analog Channel and Video Mode SelectionMode Inputs Selected Input Select Output HEX Input Select RegisterAFE Gain Control Register Video Standard RegisterCvbs and S-Video Component Video Operation Mode Register Autoswitch Mask RegisterSubaddress 03h Default 00h Color Killer Register Luminance Processing Control 1 RegisterLuminance Processing Control 3 Register Subaddress 08h Default 02h Reserved Trap filter selectLuminance Processing Control 2 Register Luminance Brightness RegisterChroma Hue Register Luminance Contrast RegisterChrominance Saturation Register Chrominance Processing Control 1 RegisterAvid Start Pixel Register Subaddress 0Eh DefaultChrominance Processing Control 2 Register WCFHsync Stop Pixel Register Avid Stop Pixel RegisterHsync Start Pixel Register Vsync Start Line RegisterVblk Start Line Register CTI Delay RegisterVsync Stop Line Register Vblk Stop Line RegisterSubaddress 2Eh Default 00h CTI coring CTI gain CTI Control RegisterSync Control Register Output Formatter 2 Register Subaddress 33h Default 40hOutput Formatter 1 Register CbCr code ReservedOutput Formatter 3 Register Output Formatter 4 Register Output Formatter 5 Register Subaddress 39h Default 00h Output Formatter 6 RegisterClear Lost Lock Detect Register Status 1 Register Read onlyColor killed Status 2 RegisterAGC Gain Status Register Subaddress 3Ch Fine gain 3Dh Coarse gainVideo Standard Status Register Gpio Input 1 RegisterGpio Input 2 Register Glco FIDAFE Coarse Gain for CH 1 Register Subaddress 46h Default 20h Cgain 1 ReservedSubaddress 47h Default 20h Cgain 2 Reserved AFE Coarse Gain for CH 2 RegisterAFE Coarse Gain for CH 3 Register Subaddress 48h Default 20h Cgain 3 ReservedSubaddress 49h Default 20h Cgain 4 Reserved AFE Coarse Gain for CH 4 RegisterAFE Fine Gain for Pb Register AFE Fine Gain for YChroma RegisterAFE Fine Gain for Pr Register Field ID Control Register Subaddress 57h Default 00hAFE Fine Gain for CVBSLuma Register FID controlReg 69h Reg 75h Mode Standard LPF Nonstandard LPF Bit Subaddress 69h Default 00hBit mode Bit and V-bit Control 1 RegisterBack-End AGC Control Register AGC Decrement Speed Control RegisterROM Version Register Subaddress 74h Default 00h Luma peak a AGC White Peak Processing RegisterLuma peak B Composite peak V Bit Control Register Lines per frame BitHorizontal Shake Increment Register VCR Trick Mode Control RegisterAGC Increment Delay Register AGC Increment Speed RegisterChip ID LSB Register Analog Output Control 1 RegisterChip ID MSB Register Cpll Speed Control RegisterAGC Decrement Delay Register Status Request RegisterVertical Line Count Register VDP TTX Filter And Mask Registers VDP TTX Filter Control Register Filter VDP Fifo Word Count RegisterNibble PassVDP Fifo Output Control Register VDP Fifo Reset RegisterVDP Fifo Interrupt Threshold Register VDP Line Number Interrupt RegisterVDP Line Start Register VDP Global Line Mode RegisterVDP Pixel Alignment Register VDP Line Stop RegisterVbus Data Access With No Vbus Address Increment Register VDP Full Field Enable RegisterVDP Full Field Mode Register Vbus Data Access With Vbus Address Increment RegisterInterrupt Raw Status 0 Register Vbus Address Access RegisterFifo Read Data Register Fifo Thrs TTX WSS VPS Vitc CC F2 CC F1Reserved Lock Interrupt Raw Status 1 RegisterInterrupt Status 0 Register Fifo fullInterrupt Status 1 Register Interrupt Mask 0 Register Subaddress F5h Default 00h Interrupt Mask 1 RegisterInterrupt Clear 0 Register Subaddress F7h Default 00h Interrupt Clear 1 RegisterVDP WSS Data Register Vbus Register DefinitionsVDP Closed Caption Data Register Subaddress ByteVDP Vitc Data Register VDP V-Chip TV Rating Block 1 RegisterVDP V-Chip TV Rating Block 2 Register None VDP V-Chip TV Rating Block 3 RegisterVDP V-CHIP Mpaa Rating Data Register TV-PGVDP General Line Mode and Line Address Register Default line mode = FFh, address = 00hVDP VPS/Gemstar Data Register VPS Read onlyInterrupt Configuration Register Analog Output Control 2 RegisterAbsolute Maximum Ratings† Crystal SpecificationsCrystal Specifications MIN NOM MAX Unit Recommended Operating ConditionsAnalog Processing and A/D Converters Electrical CharacteristicsDC Electrical Characteristics see Note Parameter Test Conditions MIN TYP MAX UnitVOH VOL TimingDataclk AVID, VS, HS, FID VC1 SDA VC0 SCLElectrical Specifications Recommended Settings ExampleAssumptions Assumptions Example Register Settings Example Register Settings Application Example −1. Example Application CircuitDesigning With PowerPADt Devices Orderable Device Status Package Pins Package Eco Plan MSL Peak TempQty Page

TVP5147M1PFP specifications

The Texas Instruments TVP5147M1PFP is a versatile video decoder that stands out in the realm of analog video processing. This device is particularly designed for high-quality video applications, making it an excellent choice for a variety of consumer and professional electronics that require reliable video decoding capabilities.

One of the main features of the TVP5147 is its ability to decode multiple video formats, including NTSC, PAL, and SECAM. This flexibility allows the decoder to seamlessly interface with various video sources from different geographic regions, providing a global solution for video applications. The TVP5147 includes advanced synchronization features, ensuring it can effectively handle video signals that may vary in timing and quality.

The device is equipped with a sophisticated 10-bit analog-to-digital converter (ADC), which enhances the precision and clarity of the digital video output. This high-resolution capability allows for improved color accuracy and detail, leading to a more lifelike video representation. Additionally, the TVP5147 utilizes advanced digital processing technologies, including noise reduction and image enhancement features, contributing to outstanding image quality even in less than ideal input conditions.

Another notable characteristic of the TVP5147M1PFP is its support for various output formats, including ITU-R BT.601 and 656, which facilitates easy integration into different systems. The device can also provide various output resolutions, catering to the needs of diverse applications ranging from standard definition to high definition displays.

In terms of connectivity, the TVP5147 offers multiple input options, including composite video, S-video, and component video interfaces. This versatility ensures that it can accommodate a wide range of video sources, from traditional VHS players to modern digital cameras. Furthermore, the integrated video control features allow for easy adjustment of parameters such as brightness, contrast, and saturation.

The power consumption of the TVP5147M1PFP is optimized for low-energy applications while maintaining high performance, making it suitable for battery-powered devices and energy-efficient designs. Overall, the Texas Instruments TVP5147M1PFP is an exceptional video decoder that blends flexibility, high quality, and advanced technology, making it a preferred choice for video processing in numerous consumer and industrial applications. Its combination of features ensures reliable performance and high-quality output, fulfilling the demands of modern multimedia environments.
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