Texas Instruments TVP5147M1PFP manual Status Request Register, Vertical Line Count Register

Page 68

Functional Description

2.11.63

Status Request Register

 

 

 

 

 

Subaddress

 

 

97h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

 

 

00h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

7

 

 

6

 

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

Capture

Capture:

Setting a 1b in this register causes the internal processor to capture the current settings of the AGC status and the vertical line count registers. Since this capture is not immediate, it is necessary to check for completion of the capture by reading the capture bit repeatedly after setting it and waiting for it to be cleared by the internal processor. Once the capture bit is 0b, the AGC status and vertical line counters (3Ch/3Dh and 9Ah/9Bh) have been updated and can be safely read in any order.

2.11.64 Vertical Line Count Register

Subaddress

9Ah

9Bh

Read only

Subaddress

7

6

5

 

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

9Ah

 

 

 

 

Vertical line [7:0]

 

 

 

 

 

 

 

 

 

 

 

9Bh

 

 

Reserved

 

 

 

Vertical line [9:8]

Vertical line [9:0] represents the detected a total number of lines from the previous frame. This can be used with nonstandard video signals such as a VCR in trick mode to synchronize downstream video circuitry.

Since this register is a double-byte register, it is necessary to capture the setting into the register to ensure that the value is not updated between reading the lower and upper bytes. In order to cause this register to capture the current settings, bit 0 of the status request register (subaddress 97h) must be set to a 1b. Once the internal processor has updated and can be read. Either byte may be read first since no further update will occur until bit 0 of 97h is set to 1b again.

2.11.65 AGC Decrement Delay Register

Subaddress

9Eh

 

 

Default

00h

7

6

5

4

3

2

1

0

AGC decrement delay [7:0]

AGC decrement delay [7:0]: Number of frames to delay gain decrements

1111 1111 = 255

0001 1110 = 30 (default)

0000 0000 = 0

60

TVP5147M1PFP

SLES140A—March 2007

Page 67 Page 69
Image 68
Page 67 Page 69
Contents Data Manual Important Notice Contents Section 11.11 Section 11.59 Example List of Illustrations List of Tables Introduction Detailed Functionality TVP5147M1 Applications Related ProductsOrdering Information Packaged DevicesFunctional Block Diagram Terminal Assignments PFP Package TOP ViewMiscellaneous Signals Terminal Functions−1. Terminal Functions Terminal Description Name NumberSync Signals VS/VBLK/GPIOIntroduction Video Input Switch Control Analog Processing and A/D ConvertersPGA ADCAnalog Input Clamping Automatic Gain ControlAnalog Video Output 5 A/D ConvertersComposite Processor Digital Video Processing1 2⋅ Decimation Filter NTSC/PAL CVBS/C−10 − dB −20 −30 −40−50 −60 −70 −10OUT Luminance ProcessingColor Transient Improvement Output Formatter Clock CircuitsReal-Time Control RTC Separate Syncs −1. Output FormatTerminal Name NumberVblk Start Line 525 First Field Video VS StartFID Vblk 622 623 624 625 First Field Video VS Start Vblk Start 23 24 Vblk Stop 336 337Avid Start Avid Stop Dataclk = 2⋅ Pixel Clock ModeHorizontal Blanking Cb0 Cr0 HS Start HS Stop −15. Horizontal Synchronization Signals for 20-Bit 422 Mode Avid Stop Dataclk = 1⋅ Pixel Clock ModeEmbedded Syncs I2C Host Interface−3. EAV and SAV Sequence D9 MSBReset and I2C Bus Address Selection Vbus Access2 I2C Operation −4. I 2C Host Interface Terminal DescriptionHost I2CVbus WSS VitcVBI System Standard Line Number Number of Bytes VBI Data Processor−6. Supported VBI System VBI Fifo and Ancillary Data in Video Stream −7. Ancillary Data Format and SequenceByte Description LSBReset and Initialization −9. Reset SequenceVBI Raw Data Output −8. VBI Raw Data Output FormatAdjusting External Syncs Register Name 2C Subaddress DefaultInternal Control Registers −10. I 2C Register SummaryVblk start line V bit control 75h 12h VCR trick mode control 76h −11. Vbus Register Summary −12. Analog Channel and Video Mode Selection Mode Inputs Selected Input Select Output HEXRegister Definitions Input Select RegisterCvbs and S-Video Component Video AFE Gain Control RegisterVideo Standard Register Subaddress 03h Default 00h Operation Mode RegisterAutoswitch Mask Register Color Killer Register Luminance Processing Control 1 RegisterSubaddress 08h Default 02h Reserved Trap filter select Luminance Processing Control 2 RegisterLuminance Processing Control 3 Register Luminance Brightness RegisterLuminance Contrast Register Chrominance Saturation RegisterChroma Hue Register Chrominance Processing Control 1 RegisterSubaddress 0Eh Default Chrominance Processing Control 2 RegisterAvid Start Pixel Register WCFAvid Stop Pixel Register Hsync Start Pixel RegisterHsync Stop Pixel Register Vsync Start Line RegisterCTI Delay Register Vsync Stop Line RegisterVblk Start Line Register Vblk Stop Line RegisterSync Control Register Subaddress 2Eh Default 00h CTI coring CTI gainCTI Control Register Subaddress 33h Default 40h Output Formatter 1 RegisterOutput Formatter 2 Register CbCr code ReservedOutput Formatter 3 Register Output Formatter 4 Register Output Formatter 5 Register Clear Lost Lock Detect Register Subaddress 39h Default 00hOutput Formatter 6 Register Status 1 Register Read onlyStatus 2 Register AGC Gain Status RegisterColor killed Subaddress 3Ch Fine gain 3Dh Coarse gainVideo Standard Status Register Gpio Input 1 RegisterGpio Input 2 Register Glco FIDSubaddress 46h Default 20h Cgain 1 Reserved Subaddress 47h Default 20h Cgain 2 ReservedAFE Coarse Gain for CH 1 Register AFE Coarse Gain for CH 2 RegisterSubaddress 48h Default 20h Cgain 3 Reserved Subaddress 49h Default 20h Cgain 4 ReservedAFE Coarse Gain for CH 3 Register AFE Coarse Gain for CH 4 RegisterAFE Fine Gain for Pr Register AFE Fine Gain for Pb RegisterAFE Fine Gain for YChroma Register Subaddress 57h Default 00h AFE Fine Gain for CVBSLuma RegisterField ID Control Register FID controlSubaddress 69h Default 00h Bit modeReg 69h Reg 75h Mode Standard LPF Nonstandard LPF Bit Bit and V-bit Control 1 RegisterROM Version Register Back-End AGC Control RegisterAGC Decrement Speed Control Register Luma peak B Composite peak Subaddress 74h Default 00h Luma peak aAGC White Peak Processing Register V Bit Control Register Lines per frame BitVCR Trick Mode Control Register AGC Increment Delay RegisterHorizontal Shake Increment Register AGC Increment Speed RegisterAnalog Output Control 1 Register Chip ID MSB RegisterChip ID LSB Register Cpll Speed Control RegisterVertical Line Count Register AGC Decrement Delay RegisterStatus Request Register VDP TTX Filter And Mask Registers VDP TTX Filter Control Register VDP Fifo Word Count Register NibbleFilter PassVDP Fifo Reset Register VDP Fifo Interrupt Threshold RegisterVDP Fifo Output Control Register VDP Line Number Interrupt RegisterVDP Global Line Mode Register VDP Pixel Alignment RegisterVDP Line Start Register VDP Line Stop RegisterVDP Full Field Enable Register VDP Full Field Mode RegisterVbus Data Access With No Vbus Address Increment Register Vbus Data Access With Vbus Address Increment RegisterVbus Address Access Register Fifo Read Data RegisterInterrupt Raw Status 0 Register Fifo Thrs TTX WSS VPS Vitc CC F2 CC F1Interrupt Raw Status 1 Register Interrupt Status 0 RegisterReserved Lock Fifo fullInterrupt Status 1 Register Interrupt Mask 0 Register Interrupt Clear 0 Register Subaddress F5h Default 00hInterrupt Mask 1 Register Subaddress F7h Default 00h Interrupt Clear 1 RegisterVbus Register Definitions VDP Closed Caption Data RegisterVDP WSS Data Register Subaddress ByteVDP V-Chip TV Rating Block 2 Register VDP Vitc Data RegisterVDP V-Chip TV Rating Block 1 Register VDP V-Chip TV Rating Block 3 Register VDP V-CHIP Mpaa Rating Data RegisterNone TV-PGVDP General Line Mode and Line Address Register Default line mode = FFh, address = 00hVDP VPS/Gemstar Data Register VPS Read onlyInterrupt Configuration Register Analog Output Control 2 RegisterCrystal Specifications Crystal Specifications MIN NOM MAX UnitAbsolute Maximum Ratings† Recommended Operating ConditionsElectrical Characteristics DC Electrical Characteristics see NoteAnalog Processing and A/D Converters Parameter Test Conditions MIN TYP MAX UnitTiming Dataclk AVID, VS, HS, FIDVOH VOL VC1 SDA VC0 SCLElectrical Specifications Assumptions Recommended SettingsExample Assumptions Example Register Settings Example Register Settings Application Example −1. Example Application CircuitDesigning With PowerPADt Devices Qty Orderable Device Status Package Pins Package Eco PlanMSL Peak Temp Page

TVP5147M1PFP specifications

The Texas Instruments TVP5147M1PFP is a versatile video decoder that stands out in the realm of analog video processing. This device is particularly designed for high-quality video applications, making it an excellent choice for a variety of consumer and professional electronics that require reliable video decoding capabilities.

One of the main features of the TVP5147 is its ability to decode multiple video formats, including NTSC, PAL, and SECAM. This flexibility allows the decoder to seamlessly interface with various video sources from different geographic regions, providing a global solution for video applications. The TVP5147 includes advanced synchronization features, ensuring it can effectively handle video signals that may vary in timing and quality.

The device is equipped with a sophisticated 10-bit analog-to-digital converter (ADC), which enhances the precision and clarity of the digital video output. This high-resolution capability allows for improved color accuracy and detail, leading to a more lifelike video representation. Additionally, the TVP5147 utilizes advanced digital processing technologies, including noise reduction and image enhancement features, contributing to outstanding image quality even in less than ideal input conditions.

Another notable characteristic of the TVP5147M1PFP is its support for various output formats, including ITU-R BT.601 and 656, which facilitates easy integration into different systems. The device can also provide various output resolutions, catering to the needs of diverse applications ranging from standard definition to high definition displays.

In terms of connectivity, the TVP5147 offers multiple input options, including composite video, S-video, and component video interfaces. This versatility ensures that it can accommodate a wide range of video sources, from traditional VHS players to modern digital cameras. Furthermore, the integrated video control features allow for easy adjustment of parameters such as brightness, contrast, and saturation.

The power consumption of the TVP5147M1PFP is optimized for low-energy applications while maintaining high performance, making it suitable for battery-powered devices and energy-efficient designs. Overall, the Texas Instruments TVP5147M1PFP is an exceptional video decoder that blends flexibility, high quality, and advanced technology, making it a preferred choice for video processing in numerous consumer and industrial applications. Its combination of features ensures reliable performance and high-quality output, fulfilling the demands of modern multimedia environments.
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