Texas Instruments TVP5147M1PFP manual VDP Pixel Alignment Register, VDP Line Start Register

Page 73

Functional Description

2.11.73 VDP Pixel Alignment Register

Subaddress

C2h−C3h

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Default

01Eh

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Subaddress

 

7

 

6

5

 

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

C2h

 

 

 

 

 

 

Pixel alignment [7:0]

 

 

 

 

 

 

 

 

 

 

 

 

 

C3h

 

 

 

 

 

Reserved

 

 

Pixel alignment [9:8]

Pixel alignment [9:8]: These registers form a 10-bit horizontal pixel position from the falling edge of horizontal sync, where the VDP controller initiates the program from one line standard to the next line standard, for example, the previous line of teletext to the next line of closed caption. This value must be set so that the switch occurs after the previous transaction has cleared the delay in the VDP, but early enough to allow the new values to be programmed before the current settings are required.

The default value is 0x1E and has been tested with every standard supported here. A new value is needed only if a custom standard is in use.

2.11.74 VDP Line Start Register

Subaddress

D6h

 

 

Default

06h

7

6

5

4

3

2

1

0

VDP line start [7:0]

VDP line start [7:0]: Set the VDP line starting address

This register must be set properly before enabling the line mode registers. The VDP processor works only the VBI region set by this register and the VDP line stop register.

2.11.75 VDP Line Stop Register

Subaddress

D7h

 

 

Default

1Bh

7

6

5

4

3

2

1

0

VDP line stop [7:0]

VDP line stop [7:0]: Set the VDP stop line address

2.11.76 VDP Global Line Mode Register

Subaddress

D8h

 

 

Default

FFh

7

6

5

4

3

2

1

0

Global line mode [7:0]

Global line mode [7:0]: VDP processing for multiple lines set by the VDP start line register at subaddress D6h and the VDP stop line register at subaddress D7h.

Global line mode register has the same bit definition as the general line mode registers. General line mode has priority over the global line mode.

SLES140A—March 2007

TVP5147M1PFP

65

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Contents Data Manual Important Notice Contents Section 11.11 Section 11.59 Example List of Illustrations List of Tables Introduction Detailed Functionality Related Products TVP5147M1 ApplicationsOrdering Information Packaged DevicesFunctional Block Diagram PFP Package TOP View Terminal AssignmentsTerminal Functions Miscellaneous Signals−1. Terminal Functions Terminal Description Name NumberVS/VBLK/GPIO Sync SignalsIntroduction Analog Processing and A/D Converters Video Input Switch ControlPGA ADCAutomatic Gain Control Analog Input ClampingAnalog Video Output 5 A/D Converters1 2⋅ Decimation Filter Digital Video ProcessingComposite Processor CVBS/C NTSC/PAL−30 −40 −10 − dB −20−50 −60 −70 −10Color Transient Improvement Luminance ProcessingOUT Real-Time Control RTC Clock CircuitsOutput Formatter −1. Output Format Separate SyncsTerminal Name NumberFID Vblk Line 525 First Field Video VS StartVblk Start Vblk Start 23 24 Vblk Stop 336 337 622 623 624 625 First Field Video VS StartHorizontal Blanking Cb0 Cr0 HS Start HS Stop Avid Stop Dataclk = 2⋅ Pixel Clock ModeAvid Start Avid Stop Dataclk = 1⋅ Pixel Clock Mode −15. Horizontal Synchronization Signals for 20-Bit 422 ModeI2C Host Interface Embedded Syncs−3. EAV and SAV Sequence D9 MSBVbus Access Reset and I2C Bus Address Selection2 I2C Operation −4. I 2C Host Interface Terminal DescriptionI2C HostVbus WSS Vitc−6. Supported VBI System VBI Data ProcessorVBI System Standard Line Number Number of Bytes −7. Ancillary Data Format and Sequence VBI Fifo and Ancillary Data in Video StreamByte Description LSB−9. Reset Sequence Reset and InitializationVBI Raw Data Output −8. VBI Raw Data Output FormatRegister Name 2C Subaddress Default Adjusting External SyncsInternal Control Registers −10. I 2C Register SummaryVblk start line V bit control 75h 12h VCR trick mode control 76h −11. Vbus Register Summary Mode Inputs Selected Input Select Output HEX −12. Analog Channel and Video Mode SelectionRegister Definitions Input Select RegisterVideo Standard Register AFE Gain Control RegisterCvbs and S-Video Component Video Autoswitch Mask Register Operation Mode RegisterSubaddress 03h Default 00h Luminance Processing Control 1 Register Color Killer RegisterLuminance Processing Control 2 Register Subaddress 08h Default 02h Reserved Trap filter selectLuminance Processing Control 3 Register Luminance Brightness RegisterChrominance Saturation Register Luminance Contrast RegisterChroma Hue Register Chrominance Processing Control 1 RegisterChrominance Processing Control 2 Register Subaddress 0Eh DefaultAvid Start Pixel Register WCFHsync Start Pixel Register Avid Stop Pixel RegisterHsync Stop Pixel Register Vsync Start Line RegisterVsync Stop Line Register CTI Delay RegisterVblk Start Line Register Vblk Stop Line RegisterCTI Control Register Subaddress 2Eh Default 00h CTI coring CTI gainSync Control Register Output Formatter 1 Register Subaddress 33h Default 40hOutput Formatter 2 Register CbCr code ReservedOutput Formatter 3 Register Output Formatter 4 Register Output Formatter 5 Register Output Formatter 6 Register Subaddress 39h Default 00hClear Lost Lock Detect Register Read only Status 1 RegisterAGC Gain Status Register Status 2 RegisterColor killed Subaddress 3Ch Fine gain 3Dh Coarse gainGpio Input 1 Register Video Standard Status RegisterGlco FID Gpio Input 2 RegisterSubaddress 47h Default 20h Cgain 2 Reserved Subaddress 46h Default 20h Cgain 1 ReservedAFE Coarse Gain for CH 1 Register AFE Coarse Gain for CH 2 RegisterSubaddress 49h Default 20h Cgain 4 Reserved Subaddress 48h Default 20h Cgain 3 ReservedAFE Coarse Gain for CH 3 Register AFE Coarse Gain for CH 4 RegisterAFE Fine Gain for YChroma Register AFE Fine Gain for Pb RegisterAFE Fine Gain for Pr Register AFE Fine Gain for CVBSLuma Register Subaddress 57h Default 00hField ID Control Register FID controlBit mode Subaddress 69h Default 00hReg 69h Reg 75h Mode Standard LPF Nonstandard LPF Bit Bit and V-bit Control 1 RegisterAGC Decrement Speed Control Register Back-End AGC Control RegisterROM Version Register AGC White Peak Processing Register Subaddress 74h Default 00h Luma peak aLuma peak B Composite peak Lines per frame Bit V Bit Control RegisterAGC Increment Delay Register VCR Trick Mode Control RegisterHorizontal Shake Increment Register AGC Increment Speed RegisterChip ID MSB Register Analog Output Control 1 RegisterChip ID LSB Register Cpll Speed Control RegisterStatus Request Register AGC Decrement Delay RegisterVertical Line Count Register VDP TTX Filter And Mask Registers VDP TTX Filter Control Register Nibble VDP Fifo Word Count RegisterFilter PassVDP Fifo Interrupt Threshold Register VDP Fifo Reset RegisterVDP Fifo Output Control Register VDP Line Number Interrupt RegisterVDP Pixel Alignment Register VDP Global Line Mode RegisterVDP Line Start Register VDP Line Stop RegisterVDP Full Field Mode Register VDP Full Field Enable RegisterVbus Data Access With No Vbus Address Increment Register Vbus Data Access With Vbus Address Increment RegisterFifo Read Data Register Vbus Address Access RegisterInterrupt Raw Status 0 Register Fifo Thrs TTX WSS VPS Vitc CC F2 CC F1Interrupt Status 0 Register Interrupt Raw Status 1 RegisterReserved Lock Fifo fullInterrupt Status 1 Register Interrupt Mask 0 Register Interrupt Mask 1 Register Subaddress F5h Default 00hInterrupt Clear 0 Register Interrupt Clear 1 Register Subaddress F7h Default 00hVDP Closed Caption Data Register Vbus Register DefinitionsVDP WSS Data Register Subaddress ByteVDP V-Chip TV Rating Block 1 Register VDP Vitc Data RegisterVDP V-Chip TV Rating Block 2 Register VDP V-CHIP Mpaa Rating Data Register VDP V-Chip TV Rating Block 3 RegisterNone TV-PGDefault line mode = FFh, address = 00h VDP General Line Mode and Line Address RegisterVPS Read only VDP VPS/Gemstar Data RegisterAnalog Output Control 2 Register Interrupt Configuration RegisterCrystal Specifications MIN NOM MAX Unit Crystal SpecificationsAbsolute Maximum Ratings† Recommended Operating ConditionsDC Electrical Characteristics see Note Electrical CharacteristicsAnalog Processing and A/D Converters Parameter Test Conditions MIN TYP MAX UnitDataclk AVID, VS, HS, FID TimingVOH VOL VC1 SDA VC0 SCLElectrical Specifications Example Recommended SettingsAssumptions Assumptions Example Register Settings Example Register Settings −1. Example Application Circuit Application ExampleDesigning With PowerPADt Devices MSL Peak Temp Orderable Device Status Package Pins Package Eco PlanQty Page

TVP5147M1PFP specifications

The Texas Instruments TVP5147M1PFP is a versatile video decoder that stands out in the realm of analog video processing. This device is particularly designed for high-quality video applications, making it an excellent choice for a variety of consumer and professional electronics that require reliable video decoding capabilities.

One of the main features of the TVP5147 is its ability to decode multiple video formats, including NTSC, PAL, and SECAM. This flexibility allows the decoder to seamlessly interface with various video sources from different geographic regions, providing a global solution for video applications. The TVP5147 includes advanced synchronization features, ensuring it can effectively handle video signals that may vary in timing and quality.

The device is equipped with a sophisticated 10-bit analog-to-digital converter (ADC), which enhances the precision and clarity of the digital video output. This high-resolution capability allows for improved color accuracy and detail, leading to a more lifelike video representation. Additionally, the TVP5147 utilizes advanced digital processing technologies, including noise reduction and image enhancement features, contributing to outstanding image quality even in less than ideal input conditions.

Another notable characteristic of the TVP5147M1PFP is its support for various output formats, including ITU-R BT.601 and 656, which facilitates easy integration into different systems. The device can also provide various output resolutions, catering to the needs of diverse applications ranging from standard definition to high definition displays.

In terms of connectivity, the TVP5147 offers multiple input options, including composite video, S-video, and component video interfaces. This versatility ensures that it can accommodate a wide range of video sources, from traditional VHS players to modern digital cameras. Furthermore, the integrated video control features allow for easy adjustment of parameters such as brightness, contrast, and saturation.

The power consumption of the TVP5147M1PFP is optimized for low-energy applications while maintaining high performance, making it suitable for battery-powered devices and energy-efficient designs. Overall, the Texas Instruments TVP5147M1PFP is an exceptional video decoder that blends flexibility, high quality, and advanced technology, making it a preferred choice for video processing in numerous consumer and industrial applications. Its combination of features ensures reliable performance and high-quality output, fulfilling the demands of modern multimedia environments.
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