Sony Singapore model Mvci, Asyo, Asyi, Avdd, Bias, Rfi, Avss, Pco, Fili, Filo, Cltv, AUX1, Adio

Page 45

Pin No.

Pin Name

I/O

Function

 

 

 

 

48

D1

I/O

 

 

 

 

 

49

D0

I/O

Data input/output for DRAM

 

 

 

 

50, 51

D2, D3

I/O

 

 

 

 

 

52

MVCI

I (S)

Clock input from an external VCO (Fixed at “L”)

 

 

 

 

53

ASYO

O

Playback EFM duplex signal output

 

 

 

 

54

ASYI

I (A)

Playback EFM comparator slice level input

 

 

 

 

55

AVDD

—

+3V power supply (Analog)

 

 

 

 

56

BIAS

I (A)

Playback EFM comparator bias current input

 

 

 

 

57

RFI

I (A)

Playback EFM RF signal input

 

 

 

 

58

AVSS

—

Ground (Analog)

 

 

 

 

59

PCO

O (3)

Phase comparison output for the recording/playback EFM master PLL

 

 

 

 

60

FILI

I (A)

Filter input for the recording/playback EFM master PLL

 

 

 

 

61

FILO

O (A)

Filter output for the recording/playback EFM master PLL

 

 

 

 

62

CLTV

I (A)

Internal VCO control voltage input for the recording/playback EFM master PLL

 

 

 

 

63

PEAK

I (A)

Light amount signal peak hold input from the CXA2523R

 

 

 

 

64

BOTM

I (A)

Light amount signal bottom hold input from the CXA2523R

 

 

 

 

65

ABCD

I (A)

Light amount signal input from the CXA2523R

 

 

 

 

66

FE

I (A)

Focus error signal input from the CXA2523R

 

 

 

 

67

AUX1

I (A)

Auxiliary A/D input

 

 

 

 

68

VC

I (A)

Middle point voltage (+1.5V) input from the CXA2523R

 

 

 

 

69

ADIO

O (A)

Monitor output of the A/D converter input signal (Not used)

 

 

 

 

70

AVDD

—

+3V power supply (Analog)

 

 

 

 

71

ADRT

I (A)

A/D converter operational range upper limit voltage input (Fixed at “H”)

 

 

 

 

72

ADRB

I (A)

A/D converter operational range lower limit voltage input (Fixed at “L”)

 

 

 

 

73

AVSS

—

Ground (Analog)

 

 

 

 

74

SE

I (A)

Sled error signal input from the CXA2523R

 

 

 

 

75

TE

I (A)

Tracking error signal input from the CXA2523R

 

 

 

 

76

DCHG

I (A)

Connected to +3V power supply

 

 

 

 

77

APC

I (A)

Error signal input for the laser digital APC (Fixed at “L”)

 

 

 

 

78

ADFG

I (S)

ADIP duplex FM signal input from the CXA2523R (22.05 ± 1 kHz)

 

 

 

 

79

F0CNT

O

Filter f0 control output to the CXA2523R

 

 

 

 

80

XLRF

O

Control latch output to the CXA2523R

 

 

 

 

81

CKRF

O

Control clock output to the CXA2523R

 

 

 

 

82

DTRF

O

Control data output to the CXA2523R

 

 

 

 

83

APCREF

O

Reference PWM output for the laser APC

 

 

 

 

84

TEST0

O

PWM output for the laser digital APC (Not used)

 

 

 

 

85

TRDR

O

Tracking servo drive PWM output (–)

 

 

 

 

• Abbreviation

EFM: Eight to Fourteen Modulation

PLL : Phase Locked Loop

VCO: Voltage Controlled Oscillator

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Page 44 Page 46
Contents MDS-JE330 SpecificationsSELF-DIAGNOSIS Function Items of Error History Mode Items and Contents Varnig Flexible Circuit Board RepairingDisassembly Table of ContentsDiagrams Exploded ViewsJIG for Checking BD Board Waveform Section Servicing NoteIOP TEORecord Precedure Forced Reset Checks Prior to Parts Replacement and AdjustmentsCriteria for Determination Measure if unsatisfactory REC/PLAYBit Binary Retry Cause Display ModeBit When Binary Higher Bits Lower Bits Hexa DetailsHexadecimal Binary Section General Location of Parts and ControlsFront Panel Section Disassembly Case and Front PanelSlider CAM SW Board and Loading Motor M103 Base Unit MBU-5A and BD BoardPrecautions for USE of Test Mode Section Test ModeSetting the Test Mode Exiting the Test ModeGroup Selecting the Test ModeNon-Volatile Memory Mode EEP Mode Operating the Continuous Playback ModeMID OUTFunctions of Other Buttons Test Mode DisplaysMeanings of Other Displays Parts Replacement and Adjustment Section Electrical AdjustmentsPrecautions for USE of Optical PICK- UP KMS-260A Precautions for Checking Laser Diode EmissinonPrecautions for Adjustments Creating Continuously Recorded DiscLaser Power Check Temperature Compensation Offset CheckChecks Prior to Repairs Specified ValueCD Error Rate Check Play Checking MO Error Rate CheckFocus Bias Check Self-Recording/playback CheckTemperature Compensation Offset Adjutment Initial Setting of Adjustment ValueLaser Power Adjustment Recording and Displaying the IOP InformationTraverse Adjustment Focus Bias Adjustment Auto Gain Control Output Level Adjustment Error Rate CheckCD Auto Gain Control Output Level Adjustment MO Auto Gain Control Output Level AdjustmentAdjusting Points and Connecting Points Circuit Boards Location Section DiagramsMDS-JE330 Block Diagrams BD SectionLD-LOVO Main SectionFor printed wiring boards For schematic diagramsWaveforms Display SectionSemiconductor Location Printed Wiring Board BD SectionSchematic Diagram BD 1/2 Section Schematic Diagram BD 2/2 Section Schematic Diagram Main 1/2 Section Schematic Diagram Main 2/2 Section Printed Wiring Board Main Section Printed Wiring Board Panel Section Schematic Diagram Panel Section Schematic Diagram BD Switch Section IC Block Diagrams Printed Wiring Board BD Switch SectionBD Section IC101 IC152 BH6511FS-E2 IC121 CXD2654RMain section IC301 UDA1341TS/N2 IC381 M5218AL IC441 LB1641IC406 M62016L IC PIN Functions IC101 RF Amplifier CXA2523AR BD boardPin No Pin Name Function MNT1 Shck MNT0 FOKMNT2 Xbusy MNT3 SlocAsyo MvciAsyi AvddFfdr TfdrFrdr FS4IC501 System Control M30620MC-400FP Main board PB-P OPT DEL OPT SEL Mode SELREC/PB SDACase and Back Panel Section Section Exploded Views6162 Front Panel Section225 226 206 205 Mechanism Section MDM-5A251 252 Base Unit Section MBU-5AResistors Section Electrical Parts ListDisplay Display KEY SW Main PIN, Connector 7P Inductor Vibrator MDS-JE330 Main SW VOL SEL
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