HCD-PX333
•BD (MD) BOARD IC151 CXD2662R
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, EFM/ACIRC ENCODER/DECODER, SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER)
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1 | MNT0 (FOK) | O | Focus OK signal output terminal “H” is output when focus is on (“L”: NG) | |||||||
Not used (open) |
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2 | MNT1 (SHOCK) | O | Track jump detection signal output to the MD mechanism controller (IC1001) | |||||||
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3 | MNT2 (XBUSY) | O | Busy monitor signal output to the MD mechanism controller (IC1001) | |||||||
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4 | MNT3 (SLOCK) | O | Spindle servo lock status monitor signal output to the MD mechanism controller (IC1001) | |||||||
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5 | SWDT | I | Writing serial data signal input from the MD mechanism controller (IC1001) | |||||||
6 | SCLK | I (S) | Serial data transfer clock signal input from the MD mechanism controller (IC1001) | |||||||
7 | XLAT | I (S) | Serial data latch pulse signal input from the MD mechanism controller (IC1001) | |||||||
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8 | SRDT | O (3) | Reading serial data signal output to the MD mechanism controller (IC1001) | |||||||
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9 |
| SENS | O (3) | Internal status (SENSE) output to the MD mechanism controller (IC1001) | ||||||
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10 |
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| I (S) | Reset signal input from the MD mechanism controller (IC1001) “L”: reset | |||||
| XRST |
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11 | SQSY | O | Subcode Q sync (SCOR) output to the MD mechanism controller (IC1001) | |||||||
“L” is output every 13.3 msec | Almost all, “H” is output | |||||||||
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12 | DQSY | O | Digital In | |||||||
(IC1001) “L” is output every 13.3 msec Almost all, “H” is output | ||||||||||
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13 |
| RECP | I | Laser power selection signal input from the MD mechanism controller (IC1001) | ||||||
| “L”: playback mode, “H”: recording mode |
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14 |
| XINT | O | Interrupt status output to the MD mechanism controller (IC1001) | ||||||
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15 |
| TX | O | Magnetic head on/off signal output to the over write head drive (IC181) | ||||||
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16 |
| OSCI | I | System clock signal (90.3168 MHz) input terminal |
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17 | OSCO | O | System clock signal (512Fs=90.3168 MHz) output terminal Not used (open) | |||||||
18 |
| XTSL | I | Input terminal for the system clock frequency setting |
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| “L”: 45.1584 MHz, “H”: 90.3168 MHz (fixed at “H” in this set) | |||||||||
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19 |
| DIN0 | I | Digital audio signal input terminal when recording mode Not used | ||||||
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20 |
| DIN1 | I | Digital audio signal input terminal when recording mode | ||||||
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21 | DOUT | O | Digital audio signal output terminal when playback mode | |||||||
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22 | DADTAI | I | Recording data input from the A/D converter (IC1005) | |||||||
23 | LRCKI | I | L/R sampling clock signal (44.1 kHz) input from the D/A converter (IC1006), A/D converter | |||||||
(IC1005) |
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24 | XBCKI | I | Bit clock signal (2.8224 MHz) input from the D/A converter (IC1006), A/D converter (IC1005) | |||||||
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25 | ADDT | I | Recording data input terminal | Not used (fixed at “L”) | ||||||
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26 | DADT | O | Playback data output terminal | Not used (open) |
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27 | LRCK | O | L/R sampling clock signal (44.1 kHz) output terminal | Not used (open) | ||||||
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28 | XBCK | O | Bit clock signal (2.8224 MHz) output terminal | Not used (open) | ||||||
29 | FS256 | O | Clock signal (11.2896 MHz) output terminal | Not used (open) | ||||||
30 | DVDD | — | Power supply terminal (+3.3V) (digital system) |
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31 to 34 | A03 to A00 | O | Address signal output to the |
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35 |
| A10 | O | Address signal output to the |
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36 to 40 | A04 to A08 | O | Address signal output to the |
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41 |
| A11 | O | Address signal output to the external | Not used (open) | |||||
42 |
| DVSS | — | Ground terminal (digital system) |
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43 |
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| O | Output enable signal output to the | “L” active | |||||
| XOE |
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* I (S) stands for schmitt input, I (A) for analog input, O (3) for
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