Appendix C: Beep and POST Codes
Code | Beeps | POST Routine Description |
|
|
|
02 |
| Verify Real Mode. |
04 |
| Get CPU type. |
06 |
| Initialize system hardware. |
08 |
| Initialize chipset registers with initial POST values. |
09 |
| Get in POST Reg. |
0A |
| Initialize CPU registers. |
0C |
| Initialize cache initial POST values. |
OE |
| Initialize I/O. |
OF |
| Initialize the localbus IDE. |
10 |
| Initialize Power Management. |
11 |
| Load alternate registers with initial POST values. |
12 |
| Jump to UserPatch0. |
14 |
| Initialize keyboard controller. |
16 | BIOS ROM checksum. | |
18 |
| 8254 timer initialization. |
1A |
| 8237 DMA controller initialization. |
1C |
| Reset Programmable Interrupt Controller. |
20 | Test DRAM refresh. | |
22 | Test 8742 Keyboard Controller. | |
24 |
| Set ES segment register to 4 GB. |
28 |
| Autosize DRAM. |
2A |
| Clear 512K base RAM. |
2C | Test 512K base address lines. | |
2E | Test 512K base memory. | |
32 |
| Test CPU |
34 |
| Test CMOS RAM. |
35 |
| Initialize alternate chipset registers. |
37 |
| Reinitialize the chipset (MB only). |
38 |
| Shadow system BIOS ROM. |
39 |
| Reinitialize the cache (MB only). |
3A |
| Autosize cache. |
3C |
| Configure advanced chipset registers. |
3D |
| Load alternate registers with CMOS values. |
40 |
| Set initial CPU speed. |
42 |
| Initialize interrupt vectors. |
44 |
| Initialize BIOS interrupts. |
46 | Check ROM copyright notice. | |
47 |
| Initialize manager for PCI Option ROMs. |
48 |
| Check video configuration against CMOS. |
49 |
| Initialize PCI bus and devices. |
|
|
|
62 |