Yamaha YMF744B (DS-1S) specifications Hardware Volume Control

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YMF744B

5. Hardware Volume Control

The hardware volume control determines the AC’97 master volume without using any software control using the external circuit listed below.

Two pins, VOLUP# for increasing the volume and VOLDW# for decreasing the volume, are used.

Push SW

1k

VOLUP#

Push SW

1k

VOLDW#

1000p1000p

DS-1S provides a shadow register for the AC’97 master volume. When the software accesses the AC’97 master volume, it is always reflected in the shadow register.

Bringing the VOLUP# pin LOW level increments the left and right-channel shadow register by +1.5dB respectively. If either one of channel shadow registers have been already set to maximum value (00000b), the corresponding channel shadow register remains in the same value, and the other channel shadow register will only be incremented. If both of channel shadow registers have been already set to maximum values, they remain in the same values.

Bringing the VOLDW# pin LOW level decrements the left and right-channel shadow register by -1.5dB respectively. If either one of channel shadow registers have been already set to minimum value (11111b), the corresponding channel shadow register remains in the same value, and the other channel shadow register will only be decremented. If both of channel shadow registers have been already set to minimum values, they remain in the same values.

The master volume for the AC’97 is updated automatically via the AC-Link by setting corresponding values to the shadow registers.

When both of the VOLUP# and VOLDW# pins are at LOW level at the same time, the MUTE bit of the shadow register is enabled to automatically set the MUTE bit of the AC’97 master volume via the AC-Link. When either one of the VOLUP# or VOLDW# pins is at LOW level, mute condition of the AC’97 is deactivated via the AC-Link. At this point of time, the master volume is set to the value before the mute. When the AC-Link is busy (in case the register is controlled by the AC’97 Control Register), shadow register values will be set to the AC’97 on the next frame. At this time, BUSY is set at the AC’97 control register.

When the master volume is changed or muted depending on the logic level transition status of the VOLUP# and VOLDW# pins, an interrupt is generated at the host. The interrupt is used to notify the driver that the master volume has been changed.

When the AC’97 is not connected or it is placed in power down mode, the shadow register values will remain in the same even if the VOLDW# and VOLUP# pins are at LOW level.

February 3, 1999

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Contents Overview FeaturesPreliminary February 3 LogosGM system level SensauraYMF744B-V 0.5mm pin pitch PIN ConfigurationYMF744B-R 0.4mm pin pitch AC’97 Interface 8-pin PIN DescriptionPCI Bus Interface 54-pin Miscellaneous 11-pin External Audio Interface 5-pinLegacy Device Interface 15-pin Reserve Pin 13-pin Power Supply 22-pinPC/PCI IRQ Block DiagramFunction Overview PCI Bus CommandTarget Device Mode Master Device Mode5C-5Fh PCI Configuration Register02-03h Device ID 04-05h Command00-01h Vendor ID 06-07h Status 0Bh Base Class Code 08h Revision ID09h Programming Interface 0Ah Sub-class Code10-13h PCI Audio Memory Base Address 0Dh Latency Timer0Eh Header Type B0................IO Read Only 18-1Bh Legacy Audio I/O Base Address Dummy for JoystickB150 ........Subsystem ID 2C-2Dh Subsystem Vendor ID2E-2Fh Subsystem ID B150 ........Subsystem Vendor ID3Eh Minimum Grant 34h Capability Register Pointer3Ch Interrupt Line 3Dh Interrupt Pin40-41h Legacy Audio Control 3Fh Maximum LatencyB108 ........SBIRQ Sound Blaster IRQ Channel Select B4................MIEN MPU401 IRQ EnableB5................I/O I/O Address Aliasing Control B76 ..........SDMA Sound Blaster DMA-8 Channel SelectB8................MAIM MPU401 Acknowledge Interrupt Mask B14..............SIEN Serialized IRQ enableB1211 ......SMOD SB DMA mode 42-43h Extended Legacy Audio Control46-47h Subsystem ID Write Register 44-45h Subsystem Vendor ID Write Register48-49h DS-1S Control Read / Write Default 0001h Access Bus Width 8, 16, 32-bitCrst AC’97 Software Reset Signal Control Wrst AC’97 Warm Reset4A-4Bh DS-1S Power Control 4C-4Dh D-DMA Slave Configuration 4E-4Fh DS-1S Power Control B12 Psacl Power Save AC-LinkPsio Power Save I/O Pad B70 ..........Capability ID Capability Identifier 50h Capability ID51h Next Item Pointer 52-53h Power Management Capabilities54-55h Power Management Control / Status 5A-5Bh DS-1S Secondary AC’97 Power Control 58-59h Acpi Mode62-63h Sound Blaster Base Address 60-61h FM Synthesizer Base AddressB150 ........Joystick Base Address 64-65h MPU401 Base Address66-67h Joystick Base Address B151 ........MPU401 Base AddressISA Compatible Device DS-1S FM Synthesizer Status Register RO FM Synthesizer BlockStatus Register FM Synthesizer Data Register Array 1 R/W FM Synthesizer Data RegisterFM Synthesizer Data Register Array 0 R/W Sound Blaster Pro Block CMD DSP CommandSB Mixer DSP Sound Blaster Pro MixerSB Mixer AC’97 Volume for MidiSbpda Sound Blaster Power Down Acknowledgement B0................SBPDR Sound Blaster Power Down RequestSE Scan Enable SM Scan ModeF4h FM Synthesizer / MPU401 Status F1h Scan In/ Out DataF2h Current FM Synthesizer Index F3h Current FM Synthesizer ArrayFfemp FM Synthesizer Empty SB IRQ Status F8h Interrupt Flag RegisterMPU401 JoystickPC/PCI DMA Emulation ProtocolDMA Serialized IRQ Interrupt RoutingHardware Volume Control Spdif Digital Audio InterfaceSclk Data Lrck Zoomed Video PortChannel Speaker System Multiple AC’97 & Multi-ChannelAC’97 Digital Docking Recommended Operating Conditions Electrical CharacteristicsAbsolute Maximum Ratings DC Characteristics Master Clock AC CharacteristicsReset PCI Clock timing PCI InterfaceMaster Clock timing for AC’97 AC’97 Master ClockAC-link timing AC-linkZoomed Video Port timing Zoomed Video PortUnit mm February 3 External DimensionsYMF744B-R Yamaha Corporation

YMF744B (DS-1S) specifications

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