YMF744B
PIN DESCRIPTION
1. PCI Bus Interface (54-pin)
Name | I/O | Type | Size | Function |
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|
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|
PCICLK | I | P |
| PCI Clock |
RST# | I | P |
| Reset |
AD[31:0] | IO | Ptr |
| Address / Data |
C/BE[3:0]# | IO | Ptr |
| Command / Byte Enable |
PAR | IO | Ptr |
| Parity |
FRAME# | IO | Pstr |
| Frame |
IRDY# | IO | Pstr |
| Initiator Ready |
TRDY# | IO | Pstr |
| Target Ready |
STOP# | IO | Pstr |
| Stop |
IDSEL | I | P |
| ID Select |
DEVSEL# | IO | Pstr |
| Device Select |
REQ# | O | Ptr |
| PCI Request |
GNT# | I | P |
| PCI Grant |
PCREQ# | O | Ptr |
| PC/PCI Request |
PCGNT# | I | P |
| PC/PCI Grant |
PERR# | IO | Pstr |
| Parity Error |
SERR# | O | Pod |
| System Error |
INTA# | O | Pod |
| Interrupt signal output for PCI bus |
SERIRQ# | IO | Ptr |
| Serialized IRQ |
CLKRUN# | IO | Ptr |
| Clock Run |
2. AC’97 Interface (8-pin)
Name | I/O | Type | Size | Function |
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|
|
|
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CRST# | O | T | 6mA | Reset signal for AC’97 |
CMCLK | O | C | 6mA | Master Clock for AC’97 (24.576MHz) |
CBCLK | I | T | - | |
CSDO | O | T | 6mA | |
CSYNC | O | T | 6mA | |
CSDI0 | I | T | - | |
CSDI2 | I | Tup | - | |
DOCKEN# | I | Tup | - | Docking Enable |