Transcend Information TS4G-32GSDHC6-P2 manual Bus Signal Levels

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TS4G-32GSDHC6-P2

SDHC Memory Card + Reader P2

 

 

 

Bus Signal Levels

As the bus can be supplied with a variable supply voltage, all signal levels are related to the supply voltage.

To meet the requirements of the JEDEC specification JESD8-1A and JESD8-7, the card input and output voltages shall be within the following specified ranges for any VDD of the allowed voltage range:

Parameter

Symbol

Min.

Max.

Unit

Remark

Output HIGH voltage

VOH

0.75* VDD

 

V

IOH = -100 µA @VDD min

Output LOW voltage

VOL

 

0.125* VDD

V

IOL = -100 µA @VDD min

Input HIGH voltage

VIH

0.625* VDD

VDD + 0.3

V

 

Input LOW voltage

VIL

VSS – 0.3

0.25* VDD

V

 

Transcend Information Inc.

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Contents TS4G-32GSDHC6-P2 Architecture Bus Signal Line Load Power Supply VoltageGeneral Current ConsumptionSingle card capacitance Bus Signal Levels Bus Timing Output Delay time during Data Transfer Mode Bus Timing High Speed Mode Output Hold time Reliability and Durability OCR register Register InformationPNM MIDOID PSN PRVMDT CRCCSD Register Fields CSD Version CsdstructureTranspeed TaacNsac Readbllen CCCReadblpartial WriteblkmisalignCsize WpgrpenableEraseblken SectorsizePermwriteprotect CopyTmpwriteprotect FileformatRCA Register Datastataftererase ScrstructureSdspec Sdbuswidths SdsecurityMechanical Dimension TS4G-32GSDHC6-P2 TS4G-32GSDHC6-P2 Features Description PlacementDimensions System RequirementsPin Identification Block DiagramPinouts Recommended Operating Conditions DC CharacteristicsDC Electrical Characteristics of 3.3V I/O