Transcend Information TS4G-32GSDHC6-P2 manual Single card capacitance

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TS4G-32GSDHC6-P2

 

 

SDHC Memory Card + Reader P2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Single card capacitance

CCARD

 

10

 

pF

 

 

Maximum signal line inductance

 

 

16

 

nH

fPP ≤ 20 MHz

 

Pull-up resistance inside card (pin1)

RDAT3

10

90

 

May be used for card

 

 

 

 

 

 

 

detection

Note that the total capacitance of CMD and DAT lines will be consist of CHOST, CBUS and one CCARD only because they are connected separately to the SD Memory Card host.

Host should consider total bus capacitance for each signal as the sum of CHOST, CBUS, and CCARD, these parameters are defined by per signal. The host can determine CHOST and CBUS so that total bus capacitance is less than the card estimated capacitance load (CL=40 pF). The SD Memory Card guarantees its bus timing when total bus capacitance is less than

maximum value of CL (40 pF).

Transcend Information Inc.

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Contents TS4G-32GSDHC6-P2 Architecture Power Supply Voltage Bus Signal Line LoadGeneral Current ConsumptionSingle card capacitance Bus Signal Levels Bus Timing Output Delay time during Data Transfer Mode Bus Timing High Speed Mode Output Hold time Reliability and Durability Register Information OCR registerOID MIDPNM PRV PSNMDT CRCCsdstructure CSD Register Fields CSD VersionNsac TaacTranspeed CCC ReadbllenReadblpartial WriteblkmisalignWpgrpenable CsizeEraseblken SectorsizeCopy PermwriteprotectTmpwriteprotect FileformatRCA Register Sdspec ScrstructureDatastataftererase Sdsecurity SdbuswidthsMechanical Dimension TS4G-32GSDHC6-P2 TS4G-32GSDHC6-P2 Description Placement FeaturesDimensions System RequirementsPinouts Block DiagramPin Identification DC Electrical Characteristics of 3.3V I/O DC CharacteristicsRecommended Operating Conditions