
1
Board Description and Memory Maps
The following table lists the features of the MVME6100.
Table | |
|
|
Feature | Description |
|
|
Processor | – Single 1.3 GHz MPC7457 processor |
| – Bus clock frequency at 133 MHz |
| – |
| – Integrated L1 and L2 cache |
|
|
L3 Cache | – 2MB using DDR SRAM |
| – Bus clock frequency at 211 MHz |
|
|
Flash | – Two banks (A & B) of soldered Intel StrataFlash devices |
| – 8 to 64MB supported on each bank |
| – Boot bank is switch selectable between banks |
| – Bank A has combination of software and hardware |
| scheme |
| – Bank B top 1MB block can be |
| software/hardware |
|
|
System Memory | – Two banks on board for up to 2GB using 256Mb or 512Mb |
| devices |
| – Bus clock frequency at 133 MHz |
|
|
Memory Controller | – Provided by Marvell MV64360 system controller |
PCI Host Bridge |
|
Dual 10/100/1000 Ethernet |
|
Interrupt Controller |
|
PCI Interface |
|
I2C Interface |
|
NVRAM | – 32KB provided by MK48T37 |
| |
Watchdog Timer |
|
|
|
– Dual 10/100/1000 Ethernet ports routed to front panel | |
Support | connectors, one optionally routed to P2 backplane |
| – Two asynchronous serial ports provided by an ST16C554D; one |
| serial port is routed to a front panel |
| serial port is optionally routed to the P2 connector for rear I/O or |
| |
|
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Computer Group Literature Center Web Site |