Emerson MVME6100 Time Base Enable Register, Quad Universal Asynchronous Receiver/Transmitter Uart

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Time Base Enable Register

Time Base Enable Register

The time base enable (TBEN) register provides the means to control the processor’s TBEN input.

Table 1-12. TBEN Register

REG

 

 

TBEN Register - 0xF1100006

 

 

 

 

 

 

 

 

 

 

 

BIT

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

FIELD

 

 

 

 

 

 

TBEN1 (NOT USED)

 

 

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

TBEN0

 

 

 

 

 

 

 

 

 

OPER

 

 

 

 

 

 

 

R/W

 

 

 

 

 

 

 

 

 

RESET

1

1

1

1

1

X

X

1

 

 

 

 

 

 

 

 

 

TBEN0

Processor 0 time base enable. When this bit is cleared, the TBEN pin of processor 0 is driven low. When this bit is set, the TBEN pin is driven high.

TBEN1

Not used on the MVME6100.

1

Quad Universal Asynchronous Receiver/Transmitter (UART)

The MVME6100 board contains one EXAR ST16C554D Quad UART device connected to the MV64360 device controller bus to provide asynchronous debug ports. The Quad UART supports up to four asynchronous serial ports of which two are used on the MVME6100. The ST16C554D is a universal asynchronous receiver and transmitter and is an enhanced UART with 16 byte FIFOs, receive trigger levels, and data rates up to 1.5 Mbps. Onboard status registers provide the user with error indications, operational status, and modem interface control. System

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Contents Programmer’s Reference Guide MVME6100 Single-Board ComputerPage Safety Summary Ground the InstrumentEMI Caution Lithium Battery CautionFlammability CE Notice European Community Limited and Restricted Rights Legend Contents Appendix a List of Figures List of Tables About This Guide Model Number DescriptionOverview of Contents Comments and SuggestionsConventions Used in This Manual BoldIntroduction OverviewNvram MVME6100 Features SummaryFeature Description PCI/PMC MVME6100 Board Layout Diagram Default Processor Memory Map Default Processor Address MapMemory Maps Processor Address Start End Size Definition29FF Ffff 41FF FfffF0FF Ffff F100 FfffMOTLoad’s Processor Memory Map MOTLoad’s Processor Address MapPCI Address Start End Size Definition Default PCI Memory MapDefault PCI Address Map MOTLoad’s PCI Memory Maps VME Memory MapSystem I/O Memory Map MOTLoad’s PCI Memory MapsDevice Bank 1 I/O Memory Map Address DefinitionM48T37V NVRAM/RTC COM 1 UartSystem Status Register System Status RegisterRefclk BankselAbortl FlashbsylFusestat SrominitBdfail EepromwpFlashawp System Status Register 2- 0xF1100001Fbootbwp FbootbwphdrTstatmask FbawphdrSystem Status Register 3- 0xF1100002 BoardresetReset Board Rsvd Presence Detect Register 10. Presence Detect RegisterIpmcprsnt EREADY1Configuration Header/Switch Register S1 11. Configuration Header/Switch RegisterPcieprsntl PMC0PL3 4 5 6 7 Time Base Enable Register Quad Universal Asynchronous Receiver/Transmitter Uart12. Tben Register TBEN0Address Offset Function 0xF1110000 13. M48T37V AccessReal-Time Clock and Nvram MV64360 Multi-Purpose Port Configuration Programming DetailsMV64360 MPP Pin Function Assignments MPP Pin Input Number Output FunctionMV64360 Reset Configuration MV64360 Power-Up Configuration Settings SromMV64360 Power-Up Configuration Settings Dram PCI1 DLLPCI0 DLL MII/GMII GMII/PCSDram PLL N TBD BADR0Flash Memory Real-Time Clock and NvramTwo-Wire Serial Interface M48T37V AccessDDR Dram Serial Presence Detect I2C Bus Device AddressingDevice Address Device Function Size A2A1A0 AddressVPD and User Configuration EEPROMs Temperature SensorMV64360 Initialization MV64360 Device Controller Bank AssignmentsMPC Bus and PCI Bus Arbitration PCI Bus 0 and PCI Bus 1 Local BusesPCI Mode/Frequency Selection Device Bank AssignmentsIdsel AD20 PCI Configuration SpaceIdsel Mapping for PCI Devices PCI Arbitration Assignments for MV64360 Asic PCI Bus 1 Local Bus PMC Expansion SlotsPCI Arbitration Assignments for MV64360 MPP Pin Assignment PCI MastersPCI Bus 0 Local Bus Devices PCI Bus 1 Local Bus PMC Expansion SlotsGroup MV64360 Edge/Level Polarity Interrupt Source MV64360 Interrupt ControllerMV64360 Interrupt Assignments PCI-PMC 0 INTC#, PMC INTA# PCI-PMC 0 INTD#, PMC INTB#MV64360 Endian Issues DS1621 Digital Thermometer and Thermostat providesDocument Title Motorola Publication Number Motorola Computer Group DocumentsTable A-1. Motorola Computer Group Documents Manufacturers’ Documents Table A-2. Manufacturers’ DocumentsDocument Title and Source Publication Number MPC7457EC/DManufacturers’ Documents Table A-2. Manufacturers’ Documents Related Specifications Table A-3. Related SpecificationsIndex