AOC P/N : 41A50-144 service manual Test Pins

Page 44

PIN #

Name

I/O

 

 

Description

 

2pxl/clk

2pxl/clk

1pxl/clk

1pxl/clk

 

 

 

 

TFT

 

 

 

8bit

6-bit

8-bit

6-bit

63

PD7

O

EG3

EG1

G3

G1

 

64

PD6

O

EG2

EG0

G2

G0

 

66

PD5

O

ER7

EG5

R7

R5

 

67

PD4

O

ER6

ER4

R6

R4

 

68

PD3

O

ER5

ER3

R5

R3

 

69

PD2

O

ER4

ER2

R4

R2

 

70

PD1

O

ER3

ER1

R3

R1

 

71

PD0

O

EG2

ER0

R2

R0

 

43

PdispE

O

This output provides a panel display enable signal that is active when flat panel

 

 

 

data is valid.

 

 

 

 

74

PHS

O

This output provides the panel line clock signal.

 

73

PVS

O

This output provides the frame start signal.

 

44

PCLKA

O

This output is used to drive the flat panel shift clock.

45

PCLKB

O

Same as PCLKA above.

 

 

 

 

 

 

The polarity and the phase of this signal are independently programmable.

75

Pbias

O

This output is used to turn on/off the panel bias power or controls backlight.

76

Ppwr

O

This output is used to control the power to a flat panel.

 

 

 

Table 5. Test Pins

 

 

 

 

PIN #

Name

I/O

Description

3

PSCAN

I

Enable automatic PCB assembly test. When this input is pulled high, the

 

 

 

automatic PCB assembly test mode is entered. An internal pull-down resistor

 

 

 

drives this input low for normal operation.

155

SCAN_IN1

I

Scan input 1 used for automatic PCB assembly tesing.

157

SCAN_IN2

I

Scan input 2 used for automatic PCB assembly tesing.

159

SCAN_OUT1

O

Scan output 1 used for automatic PCB assembly tesing.

160

SCAN_OUT2

O

Scan output 2 used for automatic PCB assembly tesing.

153

Reserved

 

 

154

Reserved

 

 

Table 6. VDD / VSS for Core Circuitry, Host Interface, and Panel/Memory Interface

 

 

 

 

PIN #

 

 

Description

65, 40, 33, 12

 

PVDD4~PVDD1 for panel / memory interface. Connect to +3.3V.

 

 

 

Must be the same voltage as the CVDD’s

149, 108, 58, 21, 11

 

SRVDD2-1, CVDD4, CVDD2-1 for core circuitry. Connect to +3.3V.

 

 

 

Must be the same voltage as the PVDD’s.

158, 151, 140, 126, 114, 72, 61,

Digital grounds for core circuiry and panel / memory interface.

49, 41, 30, 18, 8, 1

 

 

 

43

Image 44
Contents Spectrum Series SEP Table of Contents LCD-PANEL Specifications for LCD MonitorGeneral specifications Monitor Block Diagram Interface ConnectorsLCD Monitor Description AC-IN AdapterPrecautions and Notices Assembly PrecautionOperating Precautions Storage PrecautionsOperating Instructions PIN no Description REDAdjustment Method AdjustmentAdjustment Conditions and Precautions Adjust 6500 color-temperature Front Panel Control Knobs CIRCUIT-DESCRIPTION OSD-INDEX ExplanationInput not Support CHI-MEI Panel M170E1SIMPLE-INTRODUCTION about LM700 chipset MODULE-TPYE ComponentPanel Power-On Subrotine Chart Software Flow ChartSET factory mode flag Clear factory mode flagII. Main Subrotine Loop Interface-Board Trouble-Shooting chart No Screen AppearMainboard PANEL-POWER CircuitU200-DATA Output Check Oscillator Block as above Keyboard Block check POWER-BLOCK check END There is an interferences in DOS Mode Panel Luminance WAS DownInverter -MODULE Spec &Trouble Shooting Chart CorporationFunction Load Circuit M P O C O R P O R a T I O N Trouble Shooting of CHI-MEI Inverter DIVTL0037-D42 Part List Part Part Number QTY Description Supplier Remark Name Trouble Shooting Hight Voltage Protection Enbale Abnormality Transformer Abnormality Part number 80AL17-1-CH Black, 80AL17-2-CH White Check U101 PIN4NO Freq ~70KHZPage IV. Adapter BOM List Part no AL15-2-LI Reference Part Quantity Cat.NOPCB PCB for CH-1205 Revd PCS For Front Heatsink AUDIO-MODULE Trouble shooting chart No Voice OutputAudio BOM II. Sound DistortionGMZAN1 Pin Description Analog-to-Digital ConverterPIN # Name DescriptionHost Interface HIF / External On-Screen Display Clock Recovery / Time Base Conversion TFT Panel Interface PIN #Name Description 2pxl/clk 1pxl/clk TFTTest Pins System-level Block Diagram Typical Stand-alone ConfigurationOperating Modes NativeSlow Dclk ZoomSource Stand Alone DownscalingDestination Stand Alone Overall Architecture Clock Recovery CircuitFunctional Description Clock Recovery Circuit Clock Recovery Characteristics Sampling Phase AdjustmentSource Timing Generator Minimum Typical MaximumADC Characteristics Analog-to-Digital Converter 2.3.1 Pin ConnectionPin Connection for RGB Input with Hsync/Vsync Pin Connection for RGB Input with Composite SyncSync. Signal Support Display Mode SupportInput Timing Measurement Source Timing MeasurementIRQ-Generation Conditions IRQ Event Remark IRQ ControllerData Path TFT Panel Interface Timing Specification Scaling FilterGamma Table RGB OffsetPclk *1 PCLKB*4Hsync width in TFT Vsync width and display position in TFTHorizontal size in TFT Power Manager One pixel per clock mode in TFTState 0 Power Off State 1 Power OnState 2 Panel Drive Enabled State 3 Panel Fully ActivePanel Interface Drive Strength Host InterfacePanel Interface Pad Drive Strength Value 4 bits Drive Strength in mATiming Diagram of the gmZAN1 Serial Communication Serial Communication ProtocolOn-Screen Display Control GmZAN1 Serial Channel Specification Parameter Min Typ MaxMulti-Function Bus MFB OSD Color Map On-Chip OSD ControllerTclk Specification Tclk InputElectrical Characteristics DC Electrical Characteristic Parameter Min Typ MaxAbsolute Ratings Parameter Min Typ Max PvddMechanical of Cabinet Front DIS-ASSEMBLY Parts List of Cabinet T780KMGHBAA0A SpecificationParts List of Cabinet continue Parts List of Conversion Board Location CBPC780GM SpecificationLocation AI780GM Specification Location AI780GM SMD EC 22UF 16V 85C Csize Parts List of KEY PC Board KEPC780EKParts List of DC-POWER Board Parts List of Audio BoardInverter Module Power System and Consumption CurrentAdapter Module PCB Layout Schematic Diagram TOP-LEVEL FlowII. GMZAN1 Block Lvds Block MCU Block Power Block Adapter Schematic CH-1205 KBL405GC1,C2,C4 --- 1uF/50V

P/N : 41A50-144 specifications

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