AOC P/N : 41A50-144 service manual Clock Recovery Circuit

Page 49

The SCLK frequency (1/SCLK period) can be set to the range of 10-to-135 MHz. Using the DDS (direct digital synthesis) technology the clock recovery circuit can generate any SCLK clock frequency within this range.

The pixel clock (DCLK or destination clock) is used to drive a panel when the panel clock is different from SCLK (or SCLK/2). It is generated by a circuit virtually identical to the clock recovery circuit. The difference is that DCLK is locked to SCLK while SCLK is locked to the Hsync input. DCLK frequency divided by N is locked to SCLK frequency divided by M. The value M and N are calculated and programmed in the register by firmware. The value M should be close to the Source Htotal value.

Figure 4. Clock Recovery Circuit

Sample

Hsync Phase

Delay

DDS Digital
Clock
Synthesis
	DDS Output
Course	Analog
Adjust	PLL & VCO
Fine
Adjust
	PLL
	Divider
	÷ m
	Source
	Horizontal
	Total Divider

VCO

Output

Prescaler ÷ 2 (or 1)

Clock

Divider SCLK

÷ n

TCLK

Analog

PLL & VCO

Post Scale

÷ 2 (or 1)

RCLK

PLL Divider ÷ n (2 to 8)

PLL Divider

÷ 2 (or 1)

48

Image 49

Contents

Spectrum Series SEP Table of Contents General specifications Specifications for LCD MonitorLCD-PANEL Interface Connectors Monitor Block DiagramLCD Monitor Description AC-IN AdapterAssembly Precaution Precautions and NoticesOperating Precautions Storage PrecautionsPIN no Description RED Operating InstructionsAdjustment Conditions and Precautions AdjustmentAdjustment Method Adjust 6500 color-temperature Front Panel Control Knobs OSD-INDEX Explanation CIRCUIT-DESCRIPTIONInput not Support CHI-MEI Panel M170E1MODULE-TPYE Component SIMPLE-INTRODUCTION about LM700 chipsetPanel Software Flow Chart Power-On Subrotine ChartSET factory mode flag Clear factory mode flagII. Main Subrotine Loop No Screen Appear Interface-Board Trouble-Shooting chartU200-DATA Output PANEL-POWER CircuitMainboard Check Oscillator Block as above Keyboard Block check POWER-BLOCK check END Panel Luminance WAS Down There is an interferences in DOS ModeCorporation Inverter -MODULE Spec &Trouble Shooting ChartFunction Load Circuit M P O C O R P O R a T I O N Trouble Shooting of CHI-MEI Inverter DIVTL0037-D42 Part List Part Part Number QTY Description Supplier Remark Name Trouble Shooting Hight Voltage Protection Enbale Abnormality Transformer Abnormality Check U101 PIN4NO Freq ~70KHZ Part number 80AL17-1-CH Black, 80AL17-2-CH WhitePage Reference Part Quantity Cat.NO IV. Adapter BOM List Part no AL15-2-LIPCB PCB for CH-1205 Revd PCS For Front Heatsink No Voice Output AUDIO-MODULE Trouble shooting chartII. Sound Distortion Audio BOMGMZAN1 Analog-to-Digital Converter Pin DescriptionPIN # Name DescriptionHost Interface HIF / External On-Screen Display Clock Recovery / Time Base Conversion PIN # TFT Panel InterfaceName Description 2pxl/clk 1pxl/clk TFTTest Pins Typical Stand-alone Configuration System-level Block DiagramNative Operating ModesSlow Dclk ZoomDestination Stand Alone DownscalingSource Stand Alone Functional Description Clock Recovery CircuitOverall Architecture Clock Recovery Circuit Sampling Phase Adjustment Clock Recovery CharacteristicsSource Timing Generator Minimum Typical MaximumAnalog-to-Digital Converter 2.3.1 Pin Connection ADC CharacteristicsPin Connection for RGB Input with Hsync/Vsync Pin Connection for RGB Input with Composite SyncDisplay Mode Support Sync. Signal SupportInput Timing Measurement Source Timing MeasurementData Path IRQ ControllerIRQ-Generation Conditions IRQ Event Remark Scaling Filter TFT Panel Interface Timing SpecificationGamma Table RGB OffsetPCLKB*4 Pclk *1Horizontal size in TFT Vsync width and display position in TFTHsync width in TFT One pixel per clock mode in TFT Power ManagerState 1 Power On State 0 Power OffState 2 Panel Drive Enabled State 3 Panel Fully ActiveHost Interface Panel Interface Drive StrengthPanel Interface Pad Drive Strength Value 4 bits Drive Strength in mASerial Communication Protocol Timing Diagram of the gmZAN1 Serial CommunicationMulti-Function Bus MFB GmZAN1 Serial Channel Specification Parameter Min Typ MaxOn-Screen Display Control On-Chip OSD Controller OSD Color MapTclk Input Tclk SpecificationDC Electrical Characteristic Parameter Min Typ Max Electrical CharacteristicsAbsolute Ratings Parameter Min Typ Max PvddMechanical of Cabinet Front DIS-ASSEMBLY T780KMGHBAA0A Specification Parts List of CabinetParts List of Cabinet continue Location CBPC780GM Specification Parts List of Conversion BoardLocation AI780GM Specification Location AI780GM SMD EC 22UF 16V 85C Csize KEPC780EK Parts List of KEY PC BoardParts List of Audio Board Parts List of DC-POWER BoardAdapter Module Power System and Consumption CurrentInverter Module PCB Layout TOP-LEVEL Flow Schematic DiagramII. GMZAN1 Block Lvds Block MCU Block Power Block KBL405G Adapter Schematic CH-1205C1,C2,C4 --- 1uF/50V