AOC P/N : 41A50-144 service manual Operating Modes, Native, Slow Dclk, Zoom

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1.5 Operating Modes

The Source Clock (also called SCLK in this document) and the Panel Clock are defined as follows:

zThe Source Clock is the sample clock regenerated from the input Hsync timing (called clock recovery) by SCLK DDS (direct digital synthesis) and the PLL.

zThe Panel Clock is the timing clock for panel data at the single pixel per clock rate. The actual PCLK to the panel may be one-half of this frequency for double-pixel panel data format. When its frequency is different from that of source clock, the panel clock is generated by Destination Clock (or DCLK) DDS/PLL.

There are six display modes: Native, Slow DCLK, Zoom, Downscaling, Destination Stand Alone, and Source Stand Alone.

Each mode is unique in terms of:

zInput video resolution vs. panel resolution

zSource Clock frequency / Panel Clock frequency ratio

zSource Hsync frequency / Panel Hsync frequenc ratio

zData source (analog RGB, panel background color, on-chip pattern generator

1.5.1 Native

Panel Clock frequency = Source Clock frequency

Panel Hsync frequency = Input Hsync frequency

Panel Vsync frequency = Input Vsync frequency

This mode is used when the input resolution is the same as the panel resolution and the input data clock frequency is within the panel clock frequency specification of the panel being used.

1.5.2 Slow DCLK

Panel Clock frequency < Source Clock frequency

Panel Hsync frequency = Input Hsync frequency

Panel Vsync frequency = Input Vsync frequency

This mode is used when the input resolution is the same as the panel resolution, but the input data clock frequency is exceeds the panel clock frequency specification of the panel being used. The panel clock is scaled to the Source Clock, and the internal data buffers are used to spread out the timing of the input data by making use of the large CRT blanking time to extends the panel horizontal display time.

1.5.3 Zoom

Panel Clock frequency > Source Clock frequency

Panel Hsync frequency > Input Hsync frequency

Panel Vsync frequency = Input Vsync frequency

This mode is used when the input resolution is less than the panel resolution. The input data clock is then locked to the pnael clock, which is at a higher frequency. The input data is zoomed to the panel resolution.

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Contents Spectrum Series SEP Table of Contents General specifications Specifications for LCD MonitorLCD-PANEL LCD Monitor Description Monitor Block DiagramInterface Connectors AC-IN AdapterOperating Precautions Precautions and NoticesAssembly Precaution Storage PrecautionsOperating Instructions PIN no Description REDAdjustment Conditions and Precautions AdjustmentAdjustment Method Adjust 6500 color-temperature Front Panel Control Knobs Input not Support CIRCUIT-DESCRIPTIONOSD-INDEX Explanation CHI-MEI Panel M170E1SIMPLE-INTRODUCTION about LM700 chipset MODULE-TPYE ComponentPanel SET factory mode flag Power-On Subrotine ChartSoftware Flow Chart Clear factory mode flagII. Main Subrotine Loop Interface-Board Trouble-Shooting chart No Screen AppearU200-DATA Output PANEL-POWER CircuitMainboard Check Oscillator Block as above Keyboard Block check POWER-BLOCK check END There is an interferences in DOS Mode Panel Luminance WAS DownInverter -MODULE Spec &Trouble Shooting Chart CorporationFunction Load Circuit M P O C O R P O R a T I O N Trouble Shooting of CHI-MEI Inverter DIVTL0037-D42 Part List Part Part Number QTY Description Supplier Remark Name Trouble Shooting Hight Voltage Protection Enbale Abnormality Transformer Abnormality Part number 80AL17-1-CH Black, 80AL17-2-CH White Check U101 PIN4NO Freq ~70KHZPage IV. Adapter BOM List Part no AL15-2-LI Reference Part Quantity Cat.NOPCB PCB for CH-1205 Revd PCS For Front Heatsink AUDIO-MODULE Trouble shooting chart No Voice OutputAudio BOM II. Sound DistortionGMZAN1 PIN # Pin DescriptionAnalog-to-Digital Converter Name DescriptionHost Interface HIF / External On-Screen Display Clock Recovery / Time Base Conversion Name Description 2pxl/clk 1pxl/clk TFT Panel InterfacePIN # TFTTest Pins System-level Block Diagram Typical Stand-alone ConfigurationSlow Dclk Operating ModesNative ZoomDestination Stand Alone DownscalingSource Stand Alone Functional Description Clock Recovery CircuitOverall Architecture Clock Recovery Circuit Source Timing Generator Clock Recovery CharacteristicsSampling Phase Adjustment Minimum Typical MaximumPin Connection for RGB Input with Hsync/Vsync ADC CharacteristicsAnalog-to-Digital Converter 2.3.1 Pin Connection Pin Connection for RGB Input with Composite SyncInput Timing Measurement Sync. Signal SupportDisplay Mode Support Source Timing MeasurementData Path IRQ ControllerIRQ-Generation Conditions IRQ Event Remark Gamma Table TFT Panel Interface Timing SpecificationScaling Filter RGB OffsetPclk *1 PCLKB*4Horizontal size in TFT Vsync width and display position in TFTHsync width in TFT Power Manager One pixel per clock mode in TFTState 2 Panel Drive Enabled State 0 Power OffState 1 Power On State 3 Panel Fully ActivePanel Interface Pad Drive Strength Panel Interface Drive StrengthHost Interface Value 4 bits Drive Strength in mATiming Diagram of the gmZAN1 Serial Communication Serial Communication ProtocolMulti-Function Bus MFB GmZAN1 Serial Channel Specification Parameter Min Typ MaxOn-Screen Display Control OSD Color Map On-Chip OSD ControllerTclk Specification Tclk InputAbsolute Ratings Parameter Min Typ Max Electrical CharacteristicsDC Electrical Characteristic Parameter Min Typ Max PvddMechanical of Cabinet Front DIS-ASSEMBLY Parts List of Cabinet T780KMGHBAA0A SpecificationParts List of Cabinet continue Parts List of Conversion Board Location CBPC780GM SpecificationLocation AI780GM Specification Location AI780GM SMD EC 22UF 16V 85C Csize Parts List of KEY PC Board KEPC780EKParts List of DC-POWER Board Parts List of Audio BoardAdapter Module Power System and Consumption CurrentInverter Module PCB Layout Schematic Diagram TOP-LEVEL FlowII. GMZAN1 Block Lvds Block MCU Block Power Block Adapter Schematic CH-1205 KBL405GC1,C2,C4 --- 1uF/50V

P/N : 41A50-144 specifications

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