![](/images/new-backgrounds/1249440/249440111x1.webp)
Figure 7. timing Diagrams of the TFT Panel Interface (One pixel per clock)
(a) Vertical size in TFT
PVS
PHS
PDE
t1
t3t5
t2
(b) Vsync width and display position in TFT
PVS
t4
t18
t19
PHS
RGBs
t6
(c) Horizontal size in TFT
| t10 |
PHS | t7 |
| |
PCLK |
|
PDE |
| t11 |
|
|
|
| |
| t12 | t8 | t9 |
RGB data from |
| ||
|
|
| |
data paths |
|
|
|
|
| Panel Background Color Displayed |
|
(d) Hsync width in TFT
|
|
| t10 |
| t13 | t16 | t16 |
|
| ||
t14 | t15 |
|
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