AOC P/N : 41A50-144 service manual Downscaling, Destination Stand Alone, Source Stand Alone

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1.5.4 Downscaling

Panel Clock frequency < Source Clock frequency

Panel Hsync frequency < Input Hsync frequency

Panel Vsync frequency = Input Vsync frequency

This mode is used when the input resolution is greater than the panel resolution, to provide enough of a display to enable the user to recover to a supported resolution. The input clock is operated at a frequency less than that of the input pixel rate(under-sampled horizontally) and the scaling filter is used to drop input lines. In this mode, zoom scaling must be disabled

1.5.5 Destination Stand Alone

Panel Clock = DCLK in open loop (not locked)

Panel Hsync frequency = DCLK frequency / (Destination Htotal register value)

Panel Vsync frequency = DCLK frequency / (Dest. Htotal register value * Dest. Vtotal register value)

This mode is used when the input is changing or not available. The OSD may still be used as in all other display modes and stable panel timing signals are produced. This mode may be automatically set when the gmZAN1 detects input timing changes that could cause out- of-spec operation of the panel.

1.5.6 Source Stand Alone

Panel Clock = DCLK in open loop (not locked to input Hsync)

Panel Hsync frequency = SCLK frequency / (Source Htotal register value)

Panel Vsync frequency = SCLK frequency / (Source Htotal register value *Source Vtotal register value)

This mode is used to display the pattern generator data. This mode may be useful for testing an LCD panel on the manufacturing line (color temperature calibration, etc.).

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Contents

Spectrum Series SEP Table of Contents LCD-PANEL Specifications for LCD MonitorGeneral specifications AC-IN Adapter Monitor Block DiagramInterface Connectors LCD Monitor DescriptionStorage Precautions Precautions and NoticesAssembly Precaution Operating PrecautionsPIN no Description RED Operating InstructionsAdjustment Method AdjustmentAdjustment Conditions and Precautions Adjust 6500 color-temperature Front Panel Control Knobs CHI-MEI Panel M170E1 CIRCUIT-DESCRIPTIONOSD-INDEX Explanation Input not SupportMODULE-TPYE Component SIMPLE-INTRODUCTION about LM700 chipsetPanel Clear factory mode flag Power-On Subrotine ChartSoftware Flow Chart SET factory mode flagII. Main Subrotine Loop No Screen Appear Interface-Board Trouble-Shooting chartMainboard PANEL-POWER CircuitU200-DATA Output Check Oscillator Block as above Keyboard Block check POWER-BLOCK check END Panel Luminance WAS Down There is an interferences in DOS ModeCorporation Inverter -MODULE Spec &Trouble Shooting ChartFunction Load Circuit M P O C O R P O R a T I O N Trouble Shooting of CHI-MEI Inverter DIVTL0037-D42 Part List Part Part Number QTY Description Supplier Remark Name Trouble Shooting Hight Voltage Protection Enbale Abnormality Transformer Abnormality Check U101 PIN4NO Freq ~70KHZ Part number 80AL17-1-CH Black, 80AL17-2-CH WhitePage Reference Part Quantity Cat.NO IV. Adapter BOM List Part no AL15-2-LIPCB PCB for CH-1205 Revd PCS For Front Heatsink No Voice Output AUDIO-MODULE Trouble shooting chartII. Sound Distortion Audio BOMGMZAN1 Name Description Pin DescriptionAnalog-to-Digital Converter PIN #Host Interface HIF / External On-Screen Display Clock Recovery / Time Base Conversion TFT TFT Panel Interface PIN # Name Description 2pxl/clk 1pxl/clkTest Pins Typical Stand-alone Configuration System-level Block DiagramZoom Operating ModesNative Slow DclkSource Stand Alone DownscalingDestination Stand Alone Overall Architecture Clock Recovery CircuitFunctional Description Clock Recovery Circuit Minimum Typical Maximum Clock Recovery CharacteristicsSampling Phase Adjustment Source Timing GeneratorPin Connection for RGB Input with Composite Sync ADC CharacteristicsAnalog-to-Digital Converter 2.3.1 Pin Connection Pin Connection for RGB Input with Hsync/VsyncSource Timing Measurement Sync. Signal SupportDisplay Mode Support Input Timing MeasurementIRQ-Generation Conditions IRQ Event Remark IRQ ControllerData Path RGB Offset TFT Panel Interface Timing SpecificationScaling Filter Gamma TablePCLKB*4 Pclk *1Hsync width in TFT Vsync width and display position in TFTHorizontal size in TFT One pixel per clock mode in TFT Power ManagerState 3 Panel Fully Active State 0 Power OffState 1 Power On State 2 Panel Drive EnabledValue 4 bits Drive Strength in mA Panel Interface Drive StrengthHost Interface Panel Interface Pad Drive StrengthSerial Communication Protocol Timing Diagram of the gmZAN1 Serial CommunicationOn-Screen Display Control GmZAN1 Serial Channel Specification Parameter Min Typ MaxMulti-Function Bus MFB On-Chip OSD Controller OSD Color MapTclk Input Tclk SpecificationPvdd Electrical CharacteristicsDC Electrical Characteristic Parameter Min Typ Max Absolute Ratings Parameter Min Typ MaxMechanical of Cabinet Front DIS-ASSEMBLY T780KMGHBAA0A Specification Parts List of CabinetParts List of Cabinet continue Location CBPC780GM Specification Parts List of Conversion BoardLocation AI780GM Specification Location AI780GM SMD EC 22UF 16V 85C Csize KEPC780EK Parts List of KEY PC BoardParts List of Audio Board Parts List of DC-POWER BoardInverter Module Power System and Consumption CurrentAdapter Module PCB Layout TOP-LEVEL Flow Schematic DiagramII. GMZAN1 Block Lvds Block MCU Block Power Block KBL405G Adapter Schematic CH-1205C1,C2,C4 --- 1uF/50V