Sony 4-216-840-0 MNT2 Xbusy, Xlat, Srdt, Sens, Xrst, Sqsy, Dqsy, Recp, Osci, Osco, Xtsl, Lrcki

Page 31

•BD BOARD IC121 CXD2654R

(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, EFM/ACIRC ENCODER/DECODER, SHOCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER)

Pin No.

 

Pin Name

I/O

 

Description

 

 

 

 

 

 

 

 

1

 

MNT0 (FOK)

O

Focus OK signal output to the system controller (IC501)

 

 

“H” is output when focus is on (“L”: NG)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2

MNT1 (SHOCK)

O

Track jump detection signal output to the system controller (IC501)

 

 

 

 

 

 

 

3

MNT2 (XBUSY)

O

Busy monitor signal output to the system controller (IC501)

 

 

 

 

 

 

 

4

MNT3 (SLOCK)

O

Spindle servo lock status monitor signal output to the system controller (IC501)

 

 

 

 

 

 

5

 

SWDT

I

Writing serial data signal input from the system controller (IC501)

 

 

 

 

 

 

6

 

SCLK

I (S)

Serial data transfer clock signal input from the system controller (IC501)

 

 

 

 

 

 

7

 

XLAT

I (S)

Serial data latch pulse signal input from the system controller (IC501)

 

 

 

 

 

 

8

 

SRDT

O (3)

Reading serial data signal output to the system controller (IC501)

 

 

 

 

 

 

9

 

SENS

O (3)

Internal status (SENSE) output to the system controller (IC501)

 

 

 

 

 

 

 

10

 

XRST

I (S)

Reset signal input from the system controller (IC501)

“L”: reset

 

 

 

 

 

 

11

 

SQSY

O

Subcode Q sync (SCOR) output to the system controller (IC501)

 

“L” is output every 13.3 msec

Almost all, “H” is output

 

 

 

 

 

 

 

 

 

 

 

 

 

12

 

DQSY

O

Digital In U-bit CD format subcode Q sync (SCOR) output to the system controller (IC501)

 

“L” is output every 13.3 msec

Almost all, “H” is output

 

 

 

 

 

 

 

 

 

 

 

 

 

13

 

RECP

I

Laser power selection signal input from the system controller (IC501)

 

“L”: playback mode, “H”: recording mode

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

14

 

XINT

O

Interrupt status output to the system controller (IC501)

 

 

 

 

 

 

 

15

 

 

TX

I

Recording data output enable signal input from the system controller (IC501)

 

 

Writing data transmission timing input (Also serves as the magnetic head on/off output)

 

 

 

 

 

 

 

 

 

 

 

16

 

OSCI

I

System clock signal (512Fs=22.5792 MHz) input terminal

 

 

 

 

 

 

 

17

 

OSCO

O

System clock signal (512Fs=22.5792 MHz) output terminal

Not used (open)

 

 

 

 

 

 

 

 

18

 

XTSL

I

Input terminal for the system clock frequency setting

 

 

 

“L”: 45.1584 MHz, “H”: 22.5792 MHz (fixed at “H” in this set)

 

 

 

 

 

 

 

 

 

 

19

 

DIN0

I

Digital audio signal input terminal when recording mode (for digital optical input) Not used

 

 

 

 

 

20

 

DIN1

I

Digital audio signal input terminal when recording mode (for digital optical input)

 

 

 

 

 

 

21

 

DOUT

O

Digital audio signal output terminal when playback mode (for digital optical output)

 

Not used

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

22

 

DATAI

I

Serial data input terminal Not used (fixed at “L”)

 

 

 

 

 

 

 

 

23

 

LRCKI

I

L/R sampling clock signal (44.1 kHz) input terminal

Not used (fixed at “L”)

 

 

 

 

 

 

24

 

XBCKI

I

Bit clock signal (2.8224 MHz) input terminal

Not used (fixed at “L”)

 

 

 

 

 

 

25

 

ADDT

I

Recording data input from the A/D, D/A converter (IC301)

 

 

 

 

 

 

 

26

 

DADT

O

Playback data output to the A/D, D/A converter (IC301)

 

 

 

 

 

 

27

 

LRCK

O

L/R sampling clock signal (44.1 kHz) output to the A/D, D/A converter (IC301)

 

 

 

 

 

28

 

XBCK

O

Bit clock signal (2.8224 MHz) output to the A/D, D/A converter (IC301)

 

 

 

 

 

 

29

 

FS256

O

Clock signal (11.2896 MHz) output terminal

Not used (open)

 

 

 

 

 

 

 

30

 

DVDD

—

Power supply terminal (+3.3V) (digital system)

 

 

 

 

 

 

 

 

 

 

31 to 34

 

A03 to A00

O

Address signal output to the D-RAM (IC124)

 

 

 

 

 

 

 

 

 

35

 

A10

O

Address signal output to the external D-RAM

Not used (open)

 

 

 

 

 

 

 

 

36 to 40

 

A04 to A08

O

Address signal output to the D-RAM (IC124)

 

 

 

 

 

 

 

 

 

41

 

A11

O

Address signal output to the external D-RAM

Not used (open)

 

 

 

 

 

 

 

 

 

 

42

 

DVSS

—

Ground terminal (digital system)

 

 

 

 

 

 

 

 

 

 

 

43

 

XOE

O

Output enable signal output to the D-RAM (IC124)

“L” active

 

 

 

 

 

 

 

44

 

XCAS

O

Column address strobe signal output to the D-RAM (IC124)

“L” active

 

 

 

 

 

 

 

 

 

 

* I (S) stands for schmitt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.

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Contents MDS-JE520 SpecificationsMDM-5A SELF-DIAGNOSIS Function Items of Error History Mode Items and Contents Diagrams Table of ContentsSection Servicing Notes Varning Flexible Circuit Board RepairingIOP JIG for Checking BD Board WaveformRecord Precedure Criteria for Determination Measure if unsatisfactory Checks Prior to Parts Replacement and AdjustmentsPrecedure Retry Cause Display ModeHexadecimal nBinary Conversion Table Section General Cover Section DisassemblyFront Panel Section Mechanism Deck Section MDM-5A Main BoardBase Unit MBU-5A, BD Board Slider CAMSW BOARD, Loading Motor M103 Exiting the Test Mode Section Test ModePrecautions for USE of Test Mode Setting the Test ModeDisplay Contents Mark Group Selecting the Test ModeOUT Operating the Continuous Playback ModeNon-Volatile Memory Mode EEP Mode MIDFunctions of Other Buttons Test Mode DisplaysMeanings of Other Displays Parts Replacement and Adjustment Section Electrical AdjustmentsLaser power meter Precautions for Checking Laser Diode EmissionPrecautions for USE of Optical PICK-UP KMS-260A Precautions for AdjustmentsTraverse Check Temperature Compensation Offset CheckLaser Power Check Check Prior to RepairsSelf-Recording/playback Check Play Checking MO Error Rate CheckCD Error Rate Check Focus Bias CheckRecording and Displaying the IOP Information Initial Setting of Adjustment ValueTemperature Compensation Offset Adjustment Laser Power AdjustmentTraverse Adjustment ING CONTINUOUSLY-RECORDED Disc Focus Bias AdjustmentMO Auto Gain Control Output Level Adjustment Error Rate CheckAuto Gain Control Output Level Adjustment CD Auto Gain Control Output Level AdjustmentAdjustment Location IC PIN Function Description Section DiagramsSens MNT2 XbusyXlat SrdtAsyi XrasXWE AsyoSprd FS4Srdr SfdrRST AderByte CnvssLD-LOW STBChack LdinREC Analog REC Digital Block Diagram MD Servo Section∙ Signal Path Play Analog OUTREC Analog Block Diagram Main SectionCND Circuit Boards LocationSemiconductor Location MDS-M100 65 for Waveforms. See page 51 for IC Block Diagram Schematic Diagram BD Board 2/2 SeePrinted Wiring Board SW Board Schematic Diagram SW BoardIC152 BH6511FS-E2 IC121 CXD2654RMain Board IC301 ΜDA1341TS/N2 IC406 M62016L IC421 M5293LMDS-M100 Semiconductor Location Schematic Diagram Main Board 1/2 See page 65 for Waveform MDS-M100 Ref. No Location D741 D742 IC761 Q741 Q742 Q767 MDS-M100 Exploded Views SectionCover Section AEP, SP Chassis Section221 A-4680-409-A Holder Complete Assy Mechanism Section MDM-5A201 206 204 205 209 4-988-466-11 Spring ELECTROSTATIC, LeafBase Unit Section MBU-5A AC Select BD Section Electrical Parts ListTransistor FMW1 Short SwitchIC/TRANSISTOR CXA2523ARMain ConnectorCeramic Carbon InductorExcept US, CND Main Panel Panel SW Trans Sony Corporation
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