Texas Instruments BQ2461X Controls and Key Parameters Setting, Recommended Operating Conditions

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www.ti.comIntroduction

 

Table 1. I/O Description (continued)

 

 

 

Jack

 

Description

 

 

 

J5–GND

 

Ground

 

 

 

JP1–LOW

 

Ground

 

 

 

JP1–TTC

 

Timer capacitor pin

 

 

 

JP1–HI

 

Pull-up voltage source

 

 

 

JP2–HI

 

Pull-up voltage source

 

 

 

JP2–LEDPWR

 

LED Pull-up power line

 

 

 

JP3–VREF

 

IC reference voltage VREF

 

 

 

JP3–VPULLUP

 

Pull-up voltage source

 

 

 

JP3–EXT

 

External voltage supply from J2

 

 

 

JP4–VCC

 

Pull-up voltage source of ACDRV and BATDRV LED logic circuit

 

 

 

JP4–VCOM

 

Q7 and Q11 common source

 

 

 

JP5–HI

 

Pull-up voltage source

 

 

 

JP5–CHGEN

 

Charge enable

 

 

 

1.41.4 Controls and Key Parameters Setting

Table 2. Controls and Key Parameters Setting

Jack

 

Description

Factory Setting

 

 

 

 

TTC setting

 

JP1

1-2

: Connect TTC to GROUND (Disable termination and the safety timer)

Jumper on 2-3 (TTC and VPULLUP)

2-3

: Connect TTC to VPULLUP (Allow termination, but disable the safety time)

 

 

 

2 floating: Allow termination, CTTC sets the safety timer

 

 

 

 

JP2

The pull-up power source supplies the LEDs when on.

Jumper On

LED has no power source when off.

 

 

 

 

 

 

VPULLUP setting

Jumper On 1-2 (VPULLUP and

JP3

1-2

: Connect VPULLUP to VREF

VREF)

 

2-3

: Connect VPULLUP to VEXT

 

 

 

 

 

JP4

The pull-up voltage source of ACDRV and BATDRV LED logic circuit.

Jumper on

 

 

 

 

CHGEN setting

 

JP5

Jumper on: CHGEN to VPULLUP

Jumper Off

 

Jumper off: CHGEN is set to low by pull down resistor.

 

 

 

 

 

1.5Recommended Operating Conditions

Table 3. Recommended Operating Conditions

Symbol

Description

Min

Typ

Max

Unit

 

 

 

 

 

 

 

 

 

 

24(617)

 

Supply voltage, VIN

Input voltage from ac adapter input

5

24

28

V

 

 

 

 

(610/616/63x)

 

 

 

 

 

 

 

Battery voltage, VBAT

Voltage applied at VBAT terminal of J5

2.1 (61x)

21 (61x)

 

V

1.8 (63x)

18 (63x)

 

 

 

 

 

 

 

 

 

 

 

Supply current, IAC

Maximum input current from ac adapter

0

 

4.5

A

input

 

 

 

 

 

 

 

 

 

 

 

 

Charge current, Ichrg

Battery charge current

2

3

8

A

 

 

 

 

 

 

Operating junction

 

0

 

125

°C

temperature range, TJ

 

 

 

 

 

 

 

The bq2461x/bq2463x EVM board requires a regulated supply approximately 0.5 V minimum above the regulated voltage of the battery pack to a maximum input voltage of 28 VDC.

SLUU396A –January 2010 –Revised July 2010

bq2461x/bq2463x EVM (HPA422) Multi-Cell Synchronous Switch-Mode Charger

3

Copyright © 2010, Texas Instruments Incorporated

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Contents Users Guide O Description EVM FeaturesGeneral Description I/O DescriptionRecommended Operating Conditions 1.4 Controls and Key Parameters SettingControls and Key Parameters Setting Recommended Operating ConditionsEquipment DefinitionsMeters Equipment SetupCharge Current and AC Current Regultion DPM ProcedureAC Adapter Detection Threshold Charger Regulation VoltageCharger Cut-Off by Thermistor Power Path SelectionBill of Materials Bill of MaterialsOST PEC03SAAN JP1,JP3PEC03SAAN 00FEAACSET,CHGE ISET1,ISET GNDACDRV,/BAT DRV,/PGBoard Layout Nd Layer Rd Layer Bottom Layer Top Assembly Bottom Assembly Top Silkscreen Bottom Silkscreen Schematics Evaluation Board/Kit Important Notice FCC WarningEVM Warnings and Restrictions Rfid DSP