SUPER MICRO Computer SBI-7426T-S3 specification

Chapter 6: BIOS

Table 6-6. SuperIO Configuration Sub-menu

Menu Option

Serial Port1 Address

Serial Port2 Address

Serial Port2 Mode

Description

This option specifies the base I/O port address and the Interrupt Request address of Serial Port 1. Select Disabled to prevent the serial port from accessing any system resources. When this option is Disabled, the serial port physically becomes unavailable. Select 3F8/IRQ4 to allow the serial port to use 3F8 as its I/O port address and IRQ 4 for its interrupt address. Options are DISABLED, 3F8/IRQ4, 3E8/IRQ4 and 2E8/IRQ3.

Same as above, but options are DISABLED, 2F8/IRQ3, 3E8/IRQ4 and 2E8/IRQ3.

This setting allows the BIOS to select the mode for Serial Port 2. Options are Normal, IrDA and ASK IR.

Table 6-7. Chipset Configuration Sub-menu

Menu Option

CPU Bridge Configuration

QPI Links Speed

QPI Frequency

QPI L0s and L1

Memory

Frequency

Memory Mode

Demand

Scrubbing

Patrol Scrubbing

NUMA Support

DIMM CE Event Log

Description

This sub-menu configures CPU Bridge features

This option allows you to transition QPI links to Full-Speedor leave them in SLOW-MODEfor the QPI data transfer speed.

This option selects the desired QPI frequency. Option include Auto, 4.800 GT, 5.866 GT and 6.400 GT.

This option enables the QPI power state to low power with L0s and L1 automatically selected by the mainboard. The options are Disabled and

ENABLED.

This feature forces a DDR3 frequency slower than what the system has detected. The available options are Auto, DDR-800, FORCE DDR-1066 and FORCE DDR-1333.

This option sets the system memory mode. Options are the following:

•Independent (default) – All DIMMs are available to the operating system.

•CHANNEL MIRROR – The mainboard maintains two identical copies of all data in memory for redundancy.

•LOCKSTEP – The mainboard uses two areas of memory to run the same set of operations in parallel.

•SPARING – A preset threshold of correctable errors is used to trigger fail-over. The spare memory is put online and used as active memory in place of the failed memory.

This feature is a memory error-correction scheme whereby the processor writes corrected data back into the memory block from where it was read by the processor. The options are ENABLED or Disabled.

This feature is a memory error-correction scheme that works in the background looking for and correcting resident errors. The options are ENABLED or Disabled.

This feature allows you to enable NUMA support for your system. Options are Enabled or DISABLED.

This feature enables/disables a NUMA Correctable Error Event Log.The options are ENABLED or Disabled.

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