F i n i s a r |
Detailed 2 -Wire Serial Port Operation
This section gives a more detailed description of
The
The following bus protocol has been defined:
§Data transfer may be initiated only when the bus is not busy.
§During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as control signals.
Accordingly, the following bus conditions have been defined:
1)Bus not busy: Both data and clock lines remain HIGH.
2)Start data transfer: A change in the state of the data line from HIGH to LOW while the clock is HIGH defines a START condition.
3)Stop data transfer: A change in the state of the data line from LOW to HIGH while the clock line is HIGH defines the STOP condition.
4)Data valid: The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line can be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Figures 1 and 2 detail how data transfer is accomplished on the
Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions are not limited and are determined by the master device. The information is transferred byte
9/26/02 Revision D | Page 31 |