Texas Instruments
TAS5508-5142K7EVM 2.4Headphone Connector J700, 2.5Control Interface J40, Pin No
Net-Nameat Schematics
3.2Fault Reporting
Power Output Stage
1.1TAS5508-5142K7EVMFeatures
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Contents
June
Power Output Stage
Users Guide
TAS5508-5142K7EVMUser’s Guide
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SLEU071 -June2006
Contents
J901 and J900 Pin Numbers
Recommended Power-UpSequence
List of Figures
Integrated PurePath Digital Amplifier System
Chapter
Overview
1.1TAS5508-5142K7EVMFeatures
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1.2PCB Key Map
PCB Key Map
Overview
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PCB Key Map
Overview
SLEU071 -June2006
Chapter
System Interfaces
2.1Power Supply PSU Interface J901 and J900
Figure 2-1.Recommended Power-UpSequence
Table 2-3.J900 Pin Description
2.3Loudspeaker Connectors J101 ¼ J107
2.2PSU Control Interface J902
Table 2-2.J901 Pin Description
NET-NAMEAT SCHEMATICS
2.4Headphone Connector J700
Headphone Connector J700
NET-NAMEAT SCHEMATICS
PIN NO
NET-NAMEAT SCHEMATICS
Table 2-7.J40 Pin Description continued
Control Interface J40
Digital Audio Interface J60
NET-NAMEAT SCHEMATICS
2.6Digital Audio Interface J60
Table 2-8.J60 Pin Description
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Digital Audio Interface J60
System Interfaces
SLEU071 -June2006
Chapter
Protection
3.2Fault Reporting
Table 3-1.TAS5142 Warning/Error Signal Decoding
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Fault Reporting
Protection
SLEU071 -June2006
4.1Trademarks
Related Documentation From Texas Instruments
Chapter
FCC Warning
EVALUATION BOARD/KIT IMPORTANT NOTICE
EVM WARNINGS AND RESTRICTIONS
Applications
IMPORTANT NOTICE
Products
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