Texas Instruments TAS5508-5142K7EVM 2.4Headphone Connector J700, 2.5Control Interface J40, Pin No

Page 11
Headphone Connector (J700)

www.ti.com

Headphone Connector (J700)

2

1

(PCB￿connector￿top￿view)

Figure 2-4. J101 . . . J107 Pin Numbers

Table 2-5. J101 . . . J107 Pin Description

PIN NO.

NET-NAME AT SCHEMATICS

DESCRIPTION

1

OUT-1

Speaker negative output

2

OUT-2

Speaker positive output

2.4Headphone Connector (J700)

2

1

3

4

Figure 2-5. J700 Pin Numbers

Table 2-6. J700 Pin Description

PIN NO.

NET-NAME AT SCHEMATICS

DESCRIPTION

1

OUT-R

Right headphone output

2

GND

Ground

3

For future use

4

OUT-L

Left headphone output

2.5Control Interface (J40)

This interface connects the TAS5508-5142K7EVM board to a TI input-USB board.

Table 2-7. J40 Pin Description

PIN NO.

NET-NAME AT SCHEMATICS

DESCRIPTION

 

1

GND

Ground

 

2

RESERVED

 

3

GND

Ground

 

4

RESET

System reset (bidirectional). Activate

 

 

 

MUTE before RESET for quiet reset.

 

5

BKND-ERR

Backend error (or soft reset) provides

 

 

 

reduced click and pop reset, without

 

 

 

resetting I2C volume register settings.

 

6

MUTE

Ramp volume from any setting to

 

 

 

noiseless soft mute. Mute can also be

 

 

 

activated by I2C.

 

7

PDN

Power down. TAS5508B will go to

 

 

 

power-down state when activated.

 

8

RESERVED

 

9

RESERVED

 

10

SDA

I2C data clock

 

SLEU071 –June 2006

 

System Interfaces

11

Submit Documentation Feedback

 

 

 

Image 11
Contents June Power Output StageUsers Guide TAS5508-5142K7EVMUser’s GuideSubmit Documentation Feedback SLEU071 -June2006Contents J901 and J900 Pin Numbers Recommended Power-UpSequenceList of Figures Integrated PurePath Digital Amplifier SystemChapter Overview1.1TAS5508-5142K7EVMFeatures Submit Documentation Feedback 1.2PCB Key MapPCB Key Map OverviewSubmit Documentation Feedback PCB Key MapOverview SLEU071 -June2006Chapter System Interfaces2.1Power Supply PSU Interface J901 and J900 Figure 2-1.Recommended Power-UpSequenceTable 2-3.J900 Pin Description 2.3Loudspeaker Connectors J101 ¼ J1072.2PSU Control Interface J902 Table 2-2.J901 Pin DescriptionNET-NAMEAT SCHEMATICS 2.4Headphone Connector J700Headphone Connector J700 NET-NAMEAT SCHEMATICSPIN NO NET-NAMEAT SCHEMATICSTable 2-7.J40 Pin Description continued Control Interface J40Digital Audio Interface J60 NET-NAMEAT SCHEMATICS2.6Digital Audio Interface J60 Table 2-8.J60 Pin DescriptionSubmit Documentation Feedback Digital Audio Interface J60System Interfaces SLEU071 -June2006Chapter Protection3.2Fault Reporting Table 3-1.TAS5142 Warning/Error Signal DecodingSubmit Documentation Feedback Fault ReportingProtection SLEU071 -June20064.1Trademarks Related Documentation From Texas InstrumentsChapter FCC Warning EVALUATION BOARD/KIT IMPORTANT NOTICEEVM WARNINGS AND RESTRICTIONS Applications IMPORTANT NOTICEProducts