Texas Instruments TAS5508-5142K7EVM manual Protection, Chapter, 3.2Fault Reporting

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Protection

Chapter 3

SLEU071 – June 2006

Protection

This chapter describes the short-circuit protection and fault-reporting circuitry of the TAS5142 device.

3.1Short-Circuit Protection and Fault-Reporting Circuitry

The TAS5142 is a self-protecting device that provides fault reporting (including high-temperature protection and short-circuit protection). The TAS5142 is configured in back-end auto-recovery mode and, therefore, resets automatically after all errors (M1, M2, and M3 are set low). This means that the device will restart itself after a error occasion and report through the SD error signal.

3.2Fault Reporting

The OTW and SD outputs from the TAS5142 indicate fault conditions. Please refer to the TAS5142 Data Manual for a description of these pins.

Table 3-1. TAS5142 Warning/Error Signal Decoding

OTW

SD

DEVICE CONDITION

0

0

High-temperature error and/or high-current error

0

1

High-temperature warning

1

0

Undervoltage lockout or high-current error

1

1

Normal operation, no errors/warnings

The temperature warning signals at the TAS5508-5142K7EVM board are wired-OR to one temperature warning signal (OTW – pin 22 in control interface connector). Shutdown signals are wired-OR into one shutdown signal (SD – pin 20 in control interface connector).

The shutdown signals, together with the temperature warning signal, give chip state information as described in Table 3-1. Device fault-reporting outputs are open-drain outputs.

SLEU071 –June 2006

Protection

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Contents June Power Output StageUsers Guide TAS5508-5142K7EVMUser’s GuideSubmit Documentation Feedback SLEU071 -June2006Contents J901 and J900 Pin Numbers Recommended Power-UpSequenceList of Figures Integrated PurePath Digital Amplifier SystemChapter Overview1.1TAS5508-5142K7EVMFeatures Submit Documentation Feedback 1.2PCB Key MapPCB Key Map OverviewSubmit Documentation Feedback PCB Key MapOverview SLEU071 -June2006Chapter System Interfaces2.1Power Supply PSU Interface J901 and J900 Figure 2-1.Recommended Power-UpSequenceTable 2-3.J900 Pin Description 2.3Loudspeaker Connectors J101 ¼ J1072.2PSU Control Interface J902 Table 2-2.J901 Pin DescriptionNET-NAMEAT SCHEMATICS 2.4Headphone Connector J700Headphone Connector J700 NET-NAMEAT SCHEMATICSPIN NO NET-NAMEAT SCHEMATICSTable 2-7.J40 Pin Description continued Control Interface J40Digital Audio Interface J60 NET-NAMEAT SCHEMATICS2.6Digital Audio Interface J60 Table 2-8.J60 Pin DescriptionSubmit Documentation Feedback Digital Audio Interface J60System Interfaces SLEU071 -June2006Chapter Protection3.2Fault Reporting Table 3-1.TAS5142 Warning/Error Signal DecodingSubmit Documentation Feedback Fault ReportingProtection SLEU071 -June2006Related Documentation From Texas Instruments Chapter4.1Trademarks FCC Warning EVALUATION BOARD/KIT IMPORTANT NOTICEEVM WARNINGS AND RESTRICTIONS IMPORTANT NOTICE ProductsApplications