Texas Instruments TAS5508-5142K7EVM manual 1.2PCB Key Map, Overview, Submit Documentation Feedback

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PCB Key Map

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PCB Key Map

1.2PCB Key Map

Physical structure for the TAS5508-5142K7EVM is illustrated in Figure 1-2.

PSU

 

 

 

 

 

 

PSU

 

 

 

 

 

 

 

CONTROL

 

J107

J106

J105

 

 

J104

J102

J103

J101

 

 

 

INTERFACE

 

 

 

(J902)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(J900)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SPEAKER￿OUTPUTS

 

 

 

 

SPEAKER￿OUTPUTS

 

 

OUTPUT STAGE

CHANNEL 7

OUTPUT STAGE

CHANNEL 6

OUTPUT STAGE

CHANNEL 5

OUTPUT STAGE

CHANNEL 4

OUTPUT STAGE

CHANNEL 2

OUTPUT STAGE

CHANNEL 3

OUTPUT STAGE

CHANNEL 1

PSU INTERFACE (J901)

Gate Drive Regulator

 

 

 

 

 

 

 

TAS5508B

 

 

 

 

 

 

5V Regulator

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HEADPHONE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

OUTPUT

 

 

 

 

 

 

 

 

 

 

 

3.3V

 

 

(J700)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Regulator

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CONTROL

 

 

INPUT SIGNAL

 

 

 

 

 

 

 

 

 

 

INTERFACE (J40)

 

INTERFACE (J60)

 

 

 

Figure 1-2. Physical Structure for TAS5508-5142K7EVM (Rough Outline)

SLEU071 –June 2006

Overview

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Contents June Power Output StageUsers Guide TAS5508-5142K7EVMUser’s GuideSubmit Documentation Feedback SLEU071 -June2006Contents J901 and J900 Pin Numbers Recommended Power-UpSequence List of Figures Integrated PurePath Digital Amplifier SystemChapter Overview1.1TAS5508-5142K7EVMFeatures Submit Documentation Feedback 1.2PCB Key MapPCB Key Map OverviewSubmit Documentation Feedback PCB Key MapOverview SLEU071 -June2006Chapter System Interfaces2.1Power Supply PSU Interface J901 and J900 Figure 2-1.Recommended Power-UpSequenceTable 2-3.J900 Pin Description 2.3Loudspeaker Connectors J101 ¼ J1072.2PSU Control Interface J902 Table 2-2.J901 Pin DescriptionNET-NAMEAT SCHEMATICS 2.4Headphone Connector J700Headphone Connector J700 NET-NAMEAT SCHEMATICSPIN NO NET-NAMEAT SCHEMATICSTable 2-7.J40 Pin Description continued Control Interface J40Digital Audio Interface J60 NET-NAMEAT SCHEMATICS2.6Digital Audio Interface J60 Table 2-8.J60 Pin DescriptionSubmit Documentation Feedback Digital Audio Interface J60System Interfaces SLEU071 -June2006Chapter Protection3.2Fault Reporting Table 3-1.TAS5142 Warning/Error Signal DecodingSubmit Documentation Feedback Fault ReportingProtection SLEU071 -June2006Chapter Related Documentation From Texas Instruments4.1Trademarks FCC Warning EVALUATION BOARD/KIT IMPORTANT NOTICEEVM WARNINGS AND RESTRICTIONS Products IMPORTANT NOTICEApplications