Texas Instruments TAS5508-5142K7EVM manual Evm Warnings And Restrictions

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EVM WARNINGS AND RESTRICTIONS

It is important to operate this EVM within the input voltage range of 0 to 32 V and the output voltage range of 15 V to 20 V.

Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power.

Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM. Please consult the EVM User'sGuide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification, please contact a TI field representative.

During normal operation, some circuit components may have case temperatures greater than 75°C. The EVM is designed to operate properly with certain components above 75°C as long as the input and output ranges are maintained. These components include but are not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified using the EVM schematic located in the EVM User'sGuide. When placing measurement probes near these devices during operation, please be aware that these devices may be very warm to the touch.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

Copyright © 2006, Texas Instruments Incorporated

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Contents June Power Output StageUsers Guide TAS5508-5142K7EVMUser’s GuideSubmit Documentation Feedback SLEU071 -June2006Contents J901 and J900 Pin Numbers Recommended Power-UpSequenceList of Figures Integrated PurePath Digital Amplifier SystemChapter Overview1.1TAS5508-5142K7EVMFeatures Submit Documentation Feedback 1.2PCB Key MapPCB Key Map OverviewSubmit Documentation Feedback PCB Key MapOverview SLEU071 -June2006Chapter System Interfaces2.1Power Supply PSU Interface J901 and J900 Figure 2-1.Recommended Power-UpSequenceTable 2-3.J900 Pin Description 2.3Loudspeaker Connectors J101 ¼ J1072.2PSU Control Interface J902 Table 2-2.J901 Pin DescriptionNET-NAMEAT SCHEMATICS 2.4Headphone Connector J700Headphone Connector J700 NET-NAMEAT SCHEMATICSPIN NO NET-NAMEAT SCHEMATICSTable 2-7.J40 Pin Description continued Control Interface J40Digital Audio Interface J60 NET-NAMEAT SCHEMATICS2.6Digital Audio Interface J60 Table 2-8.J60 Pin DescriptionSubmit Documentation Feedback Digital Audio Interface J60System Interfaces SLEU071 -June2006Chapter Protection3.2Fault Reporting Table 3-1.TAS5142 Warning/Error Signal DecodingSubmit Documentation Feedback Fault ReportingProtection SLEU071 -June2006Chapter Related Documentation From Texas Instruments4.1Trademarks FCC Warning EVALUATION BOARD/KIT IMPORTANT NOTICEEVM WARNINGS AND RESTRICTIONS Products IMPORTANT NOTICEApplications