Texas Instruments TAS5508-5142K7EVM manual 7.J40 Pin Description continued, Control Interface J40

Page 12
Control Interface (J40)

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Control Interface (J40)

Table 2-7. J40 Pin Description (continued)

PIN NO.

NET-NAME AT SCHEMATICS

DESCRIPTION

11

GND

Ground

12

SCL

I2C bit clock

13

RESERVED

14

RESERVED

15

RESERVED

16

RESERVED

17

GND

Ground

18

RESERVED

19

RESERVED

20

SD

Shutdown error reporting for all

 

 

channels. Activated if TAS5142 has

 

 

high current or high temperature. See

 

 

Chapter 3, Protection.

21

SD

Shutdown reporting. Activated if one or

 

 

more TAS5142 has high current or high

 

 

temperature. Pin 21 connected to Pin

 

 

20. See Chapter 3, Protection.

22

OTW

Temperature warning. Activated if

 

 

TAS5142 has reached temperature

 

 

warning level.

23

OTW

Temperature warning. Activated if one

 

 

or more TAS5142 has reached

 

 

temperature warning level. Pin 23

 

 

connected to Pin 22.

24

HP-SEL

Headphone select. Headphone active

 

 

when LOW and inactive when HIGH. To

 

 

use this pin, <100-Ωresistor must be

 

 

placed for R50.

25

GND

Ground

26

GND

Ground

27

RESERVED

28

RESERVED

29

RESERVED

30

RESERVED

31

GND

Ground

32

GND

Ground

33

+5V

+5Vdc power supply (output)

34

+5V

+5Vdc power supply (output)

12

System Interfaces

SLEU071 –June 2006

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Contents Power Output Stage Users GuideTAS5508-5142K7EVMUser’s Guide JuneSLEU071 -June2006 Submit Documentation FeedbackContents Recommended Power-UpSequence List of FiguresIntegrated PurePath Digital Amplifier System J901 and J900 Pin NumbersOverview Chapter1.1TAS5508-5142K7EVMFeatures 1.2PCB Key Map PCB Key MapOverview Submit Documentation FeedbackPCB Key Map OverviewSLEU071 -June2006 Submit Documentation FeedbackSystem Interfaces 2.1Power Supply PSU Interface J901 and J900Figure 2-1.Recommended Power-UpSequence Chapter2.3Loudspeaker Connectors J101 ¼ J107 2.2PSU Control Interface J902Table 2-2.J901 Pin Description Table 2-3.J900 Pin Description2.4Headphone Connector J700 Headphone Connector J700NET-NAMEAT SCHEMATICS NET-NAMEAT SCHEMATICSNET-NAMEAT SCHEMATICS Table 2-7.J40 Pin Description continuedControl Interface J40 PIN NONET-NAMEAT SCHEMATICS 2.6Digital Audio Interface J60Table 2-8.J60 Pin Description Digital Audio Interface J60Digital Audio Interface J60 System InterfacesSLEU071 -June2006 Submit Documentation FeedbackProtection 3.2Fault ReportingTable 3-1.TAS5142 Warning/Error Signal Decoding ChapterFault Reporting ProtectionSLEU071 -June2006 Submit Documentation FeedbackRelated Documentation From Texas Instruments Chapter4.1Trademarks EVALUATION BOARD/KIT IMPORTANT NOTICE FCC WarningEVM WARNINGS AND RESTRICTIONS IMPORTANT NOTICE ProductsApplications