VXI Microwave Matrix, SM7100 user manual Trace RAM Start High Register 0x28 Read and Write

Page 26

VXI Technology, Inc.

Trace RAM Start High Register (0x28) — Read and Write

D15-D4

Unused

Data written to these bits have no effect and always read back as 1.

D3-D0

 

Sets the four most significant bits of the starting address of the Trace

 

RAM, allowing the available RAM to be divided into multiple traces.

 

 

Trace RAM Start Low Register (0x2A) — Read and Write

D15-D0

Sets the 16 least significant bits of the starting address of the Trace RAM, allowing the available RAM to be divided into multiple traces.

Trace RAM End High Register (0x2C) — Read and Write

D15-D4

Unused

Data written to these bits have no effect and always read back as 1.

D3-D0

 

Sets the four most significant bits of the ending address of the Trace

 

RAM, allowing the available RAM to be divided into multiple traces.

 

 

Trace RAM End Low Register (0x2E) — Read and Write

D15-D0

Sets the 16 least significant bits of the ending address of the Trace RAM, allowing the available RAM to be divided into multiple traces.

Trace RAM Address HIGH Register (0x30) — Read and Write

D15-D4

Unused

Data written to these bits have no effect and always read back as 1.

 

 

Sets and reads back the four most significant bits of the current

D3-D0

 

address of the Trace RAM, allowing the current trace RAM address to

 

 

be queried and changed.

Trace RAM Address LOW Register (0x32) — Read and Write

D15-D0

Sets and reads back the sixteen least significant bits of the current address of the Trace RAM, allowing the current trace RAM address to be queried and changed.

Trace Advance Trigger Select Register (0x34) —Write Only

D15-D8

D7-D0

Sets the TTLTRIG line or lines, which are configured as outputs, and will toggle when Trace Advance condition occurs in the module. D15 corresponds to TTLTRIG7, D14 to TTLTRIG6, … and D8 to TTLTRIG0. Setting a bit to a 1 enables the trigger line, setting a bit to 0 disables the corresponding line. All bits are set to 0 when either a soft or a hard reset is received by the module.

Sets the TTLTRIG line or lines, which are configured as inputs, and will cause a Trace Advance event to occur in the module. D7 corresponds to TTLTRIG7, D6 to TTLTRIG6, … and D0 to TTLTRIG0. Setting a bit to a 1 enables the trigger line, setting a bit to 0 disables the corresponding line. All enabled TTLTRIG lines are OR'd together to allow more than one TTLTRIG line to cause a Trace Advance event to occur. All bits are set to 0 when the module receives either a soft or a hard reset.

26

SM7100 Programming

Image 26
Contents SM7100 VXI Technology, Inc Table of Contents Certification WarrantyLimitation of Warranty Restricted Rights LegendC L a R a T I O N O F C O N F O R M I T Y EMCGeneral Safety Instructions Terms and SymbolsAvoid Electric Shock Support Resources Overview ProgrammingSMA SM7100 SpecificationsVswr Introduction Calculating System Power and Cooling RequirementsSetting the Chassis Backplane Jumpers Setting the Logical Address MSB LSBSelecting the Extended Memory Space VXI Technology, Inc SM7100 Preparation for Use Switch Configuration Front Panel Connection SM7000Return GND EXTGND SM7100 Module Configuration SM7100 Matrix Schematic Offset Hex VXI Technology, Inc SM7100 Module Configuration Register Access AddressingSmip II Register MAP A16 Offset Write FunctionDevice Type Register 0x02 Read Only ID Register 0x00 Read OnlyLogical Address Register 0x00 Write Only Status Register 0x04 Read OnlyReserved Register 0x0C Read Only Offset Register 0x06 Read and WriteReserved Register 0x0A Read Only Version Number Register 0x0E Read OnlyInterrupt Control Register 0x1C Read and Write NVM Access Resister 0x20 Read OnlyNVM Access Resister 0x20 Write Only Subclass Register 0x1E Read OnlyTrace RAM End High Register 0x2C Read and Write Trace RAM Start High Register 0x28 Read and WriteTrace RAM Start Low Register 0x2A Read and Write Trace RAM End Low Register 0x2E Read and WriteOpen Trigger Select Register 0x36 -Write Only Loop EnableTrace Enable TTL Trigger Polarity Register 0x38 -Write OnlyBoard Busy Register 0x3E Read Only Busy Trigger Control Register 0x3C Read and WriteTrigger Advance Register 0x3E Write Only Reserved Registers Read and WriteAddr AcfailnBBM/MBB Control Register Read and Write Delay Register Read and Write Relay Register Offset Writing to the RelaysVIA16SPACE Index SM7100