VXI Technology, Inc.
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| Busy Trigger Control Register (0x3C) — Read and Write | |
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| Sets the TTLTRIG Line or Lines, which are configured as outputs, and |
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| will toggle at the |
| TTLTRIG Select | ||
| … and D8 to TTLTRIG0. Setting a bit to a 1 enables the trigger line, | ||
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| setting a bit to a 0 disables the corresponding line. All bits are set to 0 |
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| when either a soft or a hard reset is received by the module. |
| Unused | Data written to these bits have no effect. The value written is read | |
| back. | ||
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| Enables the Board Busy signal received from the switch module to |
| D0 | Busy Trigger Enable | generate a trigger condition on the TTL Trigger Bus. Setting a bit to 1 |
| enables the generation of a Trigger condition, setting a bit to a 0 | ||
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| disables the corresponding line. This bit is set to 0 when either a soft |
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| or a hard reset is received by the module. |
Trigger Advance Register (0x3E) — Write Only
Unused
The act of writing to this location causes a Trace Advance event to occur in the module. The specific data written to these bits has no effect.
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| Board Busy Register (0x3E) — Read Only | ||
Unused |
| These bits always read back as 1. | ||
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| Indicates whether the SMIP II platform is a single or double wide. | |
D6 |
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| 0 | = single wide |
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| 1 | = double wide |
Unused |
| Data written to these bits have no effect. | ||
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| A 0 read from this bit indicates the relays on the switch module have | |
D0 |
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| settled, a 1 indicates that the relays on the switch module are still | |
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| changing state. |
Reserved Registers — Read and Write
Unused | Writing to these registers has no effect and will always read back as | ||
FFFF16. | |||
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28 | SM7100 Programming |